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REJ09B0309-0200
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16
H8/38099Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series H8/38099F H8/38099 H8/38098
Rev.2.00 Revision Date: Jul. 04, 2007
Rev. 2.00 Jul. 04, 2007 Page ii of xl
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 2.00 Jul. 04, 2007 Page iii of xl
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 2.00 Jul. 04, 2007 Page iv of xl
Configuration of This Manual
This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * * CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
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Preface
H8/38099 Group is single-chip microcontrollers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/38099 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcontrollers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8/38099 Group to the target users. Refer to the H8/300H Series Software Manual for a detailed description of the instruction set.
Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions, and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8/300H Series Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 24, List of Registers. Example: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communications interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right.
Bit order:
Rev. 2.00 Jul. 04, 2007 Page vi of xl
Notes: When using an on-chip emulator (E8) for H8/38099 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E8, and cannot be used. 2. Pins P16, P36, and P37 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. Area H'020000 to H'020FFF must on no account be accessed. 4. Area HFFA000 to HFFA7FF must on no account be accessed. 5. When the E8 is used, address breaks can be set as either available to the user or for use by the E8. If address breaks are set as being used by the E8, the address break control registers must not be accessed. 6. When the E8 is used, NMI is an input pin, P16 and P36 are input pins, and P37 is an output pin. 7. When on-board programming/erasing is performed in boot mode, the SCI3_1 (P41/RXD and P42/TXD) is used. 8. When using the E8, set the FROMCKSTP bit in clock halt register 1 to 1. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require (http://www.renesas.com/)
H8/38099 Group manuals:
Document Title H8/38099 Group Hardware Manual H8/300H Series Software Manual Document No. This manual REJ09B0213
User's manuals for development tools:
Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual Document No. REJ10B0058 ADE-702-037 REJ10B0024 REJ10B0026
Rev. 2.00 Jul. 04, 2007 Page vii of xl
Application notes:
Document Title H8S, H8/300 Series C/C++ Compiler Package Application Note Document No. REJ05B0464
All trademarks and registered trademarks are the property of their respective owners.
Rev. 2.00 Jul. 04, 2007 Page viii of xl
Contents
Section 1 Overview................................................................................................1
1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 3 Pin Assignment ...................................................................................................................... 4 Pin Functions ......................................................................................................................... 5
Section 2 CPU......................................................................................................11
2.1 2.2 Address Space and Memory Map ........................................................................................ 13 Register Configuration......................................................................................................... 14 2.2.1 General Registers .................................................................................................... 15 2.2.2 Program Counter (PC) ............................................................................................ 16 2.2.3 Condition-Code Register (CCR) ............................................................................. 16 Data Formats........................................................................................................................ 18 2.3.1 General Register Data Formats ............................................................................... 18 2.3.2 Memory Data Formats ............................................................................................ 20 Instruction Set ...................................................................................................................... 21 2.4.1 Table of Instructions Classified by Function .......................................................... 21 2.4.2 Basic Instruction Formats ....................................................................................... 31 Addressing Modes and Effective Address Calculation ........................................................ 32 2.5.1 Addressing Modes .................................................................................................. 32 2.5.2 Effective Address Calculation ................................................................................ 36 Basic Bus Cycle ................................................................................................................... 38 2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 38 2.6.2 On-Chip Peripheral Modules .................................................................................. 39 CPU States ........................................................................................................................... 40 Usage Notes ......................................................................................................................... 41 2.8.1 Notes on Data Access to Empty Areas ................................................................... 41 2.8.2 EEPMOV Instruction.............................................................................................. 41 2.8.3 Bit-Manipulation Instruction .................................................................................. 42
2.3
2.4
2.5
2.6
2.7 2.8
Section 3 Exception Handling .............................................................................47
3.1 3.2 Exception Sources and Vector Address ............................................................................... 48 Reset..................................................................................................................................... 49 3.2.1 Reset Exception Handling....................................................................................... 49 3.2.2 Interrupt Immediately after Reset ........................................................................... 50 Interrupts.............................................................................................................................. 51
3.3
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3.4 3.5
Stack Status after Exception Handling................................................................................. 52 Usage Notes ......................................................................................................................... 53 3.5.1 Notes on Stack Area Use ........................................................................................ 53 3.5.2 Notes on Rewriting Port Mode Registers ............................................................... 54 3.5.3 Method for Clearing Interrupt Request Flags ......................................................... 57
Section 4 Interrupt Controller.............................................................................. 59
4.1 4.2 4.3 Features................................................................................................................................ 59 Input/Output Pins................................................................................................................. 60 Register Descriptions ........................................................................................................... 60 4.3.1 Interrupt Edge Select Register (IEGR) ................................................................... 61 4.3.2 Wakeup Edge Select Register (WEGR).................................................................. 62 4.3.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 63 4.3.4 Interrupt Enable Register 2 (IENR2) ...................................................................... 64 4.3.5 Interrupt Request Register 1 (IRR1) ....................................................................... 65 4.3.6 Interrupt Request Register 2 (IRR2) ....................................................................... 66 4.3.7 Wakeup Interrupt Request Register (IWPR) .......................................................... 68 4.3.8 Interrupt Priority Registers A to F (IPRA to IPRF) ................................................ 70 4.3.9 Interrupt Mask Register (INTM) ............................................................................ 71 Interrupt Sources.................................................................................................................. 71 4.4.1 External Interrupts .................................................................................................. 71 4.4.2 Internal Interrupts ................................................................................................... 73 Interrupt Exception Handling Vector Table......................................................................... 73 Operation ............................................................................................................................. 77 4.6.1 Interrupt Exception Handling Sequence ................................................................. 79 4.6.2 Interrupt Response Times ....................................................................................... 81 Usage Notes ......................................................................................................................... 82 4.7.1 Contention between Interrupt Generation and Disabling........................................ 82 4.7.2 Instructions that Disable Interrupts......................................................................... 83 4.7.3 Interrupts during Execution of EEPMOV Instruction............................................. 83 4.7.4 IENR Clearing ........................................................................................................ 83
4.4
4.5 4.6
4.7
Section 5 Clock Pulse Generator......................................................................... 85
5.1 Register Description............................................................................................................. 86 5.1.1 SUB32k Control Register (SUB32CR)................................................................... 86 5.1.2 Oscillator Control Register (OSCCR) .................................................................... 87 System Clock Generator ...................................................................................................... 88 5.2.1 Connecting Crystal Resonator ................................................................................ 88 5.2.2 Connecting Ceramic Resonator .............................................................................. 89 5.2.3 External Clock Input Method.................................................................................. 89
5.2
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5.3
5.4
5.5
5.2.4 Selecting On-Chip Oscillator for System Clock ..................................................... 90 Subclock Generator.............................................................................................................. 91 5.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator............................................. 91 5.3.2 Pin Connection when not Using Subclock.............................................................. 92 5.3.3 How to Input the External Clock ............................................................................ 93 Prescalers ............................................................................................................................. 94 5.4.1 Prescaler S .............................................................................................................. 94 5.4.2 Prescaler W ............................................................................................................. 94 Usage Notes ......................................................................................................................... 95 5.5.1 Note on Resonators and Resonator Circuits............................................................ 95 5.5.2 Notes on Board Design ........................................................................................... 97 5.5.3 Definition of Oscillation Stabilization Wait Time .................................................. 97 5.5.4 Note on Subclock Stop State................................................................................... 98 5.5.5 Note on the Oscillation Stabilization of Resonators ............................................... 99 5.5.6 Note on Using On-Chip Power-On Reset ............................................................... 99 5.5.7 Note on Using the On-Chip Emulator..................................................................... 99
Section 6 Power-Down Modes ..........................................................................101
6.1 Register Descriptions ......................................................................................................... 102 6.1.1 System Control Register 1 (SYSCR1) .................................................................. 102 6.1.2 System Control Register 2 (SYSCR2) .................................................................. 104 6.1.3 System Control Register 3 (SYSCR3) .................................................................. 105 6.1.4 Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3) ........................................ 107 Mode Transitions and States of LSI................................................................................... 110 6.2.1 Sleep Mode ........................................................................................................... 116 6.2.2 Standby Mode ....................................................................................................... 116 6.2.3 Watch Mode.......................................................................................................... 117 6.2.4 Subsleep Mode...................................................................................................... 117 6.2.5 Subactive Mode .................................................................................................... 118 6.2.6 Active (Medium-Speed) Mode ............................................................................. 118 Direct Transition ................................................................................................................ 119 6.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode......................................................................................... 119 6.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode............... 120 6.3.3 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode .............................................................................................. 120 6.3.4 Direct Transition from Active (Medium-Speed) Mode to Subactive Mode ......... 121 6.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode............... 121 6.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ......... 122 6.3.7 Notes on External Input Signal Changes before/after Direct Transition............... 123
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6.2
6.3
6.4 6.5
Module Standby Function.................................................................................................. 123 Usage Notes ....................................................................................................................... 124 6.5.1 Standby Mode Transition and Pin States .............................................................. 124 6.5.2 Notes on External Input Signal Changes before/after Standby Mode................... 125
Section 7 ROM ..................................................................................................127
7.1 7.2 Block Configuration .......................................................................................................... 128 Register Descriptions ......................................................................................................... 129 7.2.1 Flash Memory Control Register 1 (FLMCR1) ..................................................... 129 7.2.2 Flash Memory Control Register 2 (FLMCR2) ..................................................... 130 7.2.3 Erase Block Register 1 (EBR1) ............................................................................ 131 7.2.4 Erase Block Register 2 (EBR2) ............................................................................ 132 7.2.5 Flash Memory Power Control Register (FLPWCR) ............................................. 132 7.2.6 Flash Memory Enable Register (FENR)............................................................... 133 On-Board Programming Modes......................................................................................... 133 7.3.1 Boot Mode ............................................................................................................ 134 7.3.2 Programming/Erasing in User Program Mode...................................................... 137 Using RAM to Emulate Flash Memory ............................................................................. 138 Flash Memory Programming/Erasing ................................................................................ 140 7.5.1 Program/Program-Verify ...................................................................................... 140 7.5.2 Erase/Erase-Verify................................................................................................ 143 7.5.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 143 Program/Erase Protection .................................................................................................. 145 7.6.1 Hardware Protection ............................................................................................. 145 7.6.2 Software Protection............................................................................................... 145 7.6.3 Error Protection .................................................................................................... 145 Programmer Mode ............................................................................................................. 146 Power-Down States for Flash Memory.............................................................................. 146 Notes on Setting Module Standby Mode ........................................................................... 147
7.3
7.4 7.5
7.6
7.7 7.8 7.9
Section 8 RAM ..................................................................................................149 Section 9 I/O Ports.............................................................................................151
9.1 Port 1.................................................................................................................................. 151 9.1.1 Port Data Register 1 (PDR1)................................................................................. 152 9.1.2 Port Control Register 1 (PCR1) ............................................................................ 152 9.1.3 Port Pull-Up Control Register 1 (PUCR1)............................................................ 153 9.1.4 Port Mode Register 1 (PMR1) .............................................................................. 153 9.1.5 Pin Functions ........................................................................................................ 154 9.1.6 Input Pull-Up MOS............................................................................................... 159
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9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Port 3.................................................................................................................................. 160 9.2.1 Port Data Register 3 (PDR3)................................................................................. 160 9.2.2 Port Control Register 3 (PCR3) ............................................................................ 161 9.2.3 Port Pull-Up Control Register 3 (PUCR3)............................................................ 162 9.2.4 Port Mode Register 3 (PMR3) .............................................................................. 162 9.2.5 Pin Functions ........................................................................................................ 163 9.2.6 Input Pull-Up MOS............................................................................................... 165 Port 4.................................................................................................................................. 166 9.3.1 Port Data Register 4 (PDR4)................................................................................. 166 9.3.2 Port Control Register 4 (PCR4) ............................................................................ 167 9.3.3 Port Mode Register 4 (PMR4) .............................................................................. 168 9.3.4 Pin Functions ........................................................................................................ 169 Port 5.................................................................................................................................. 170 9.4.1 Port Data Register 5 (PDR5)................................................................................. 171 9.4.2 Port Control Register 5 (PCR5) ............................................................................ 171 9.4.3 Port Pull-Up Control Register 5 (PUCR5)............................................................ 172 9.4.4 Port Mode Register 5 (PMR5) .............................................................................. 172 9.4.5 Pin Functions ........................................................................................................ 173 9.4.6 Input Pull-Up MOS............................................................................................... 174 Port 6.................................................................................................................................. 174 9.5.1 Port Data Register 6 (PDR6)................................................................................. 175 9.5.2 Port Control Register 6 (PCR6) ............................................................................ 175 9.5.3 Port Pull-Up Control Register 6 (PUCR6)............................................................ 176 9.5.4 Pin Functions ........................................................................................................ 176 9.5.5 Input Pull-Up MOS............................................................................................... 177 Port 7.................................................................................................................................. 178 9.6.1 Port Data Register 7 (PDR7)................................................................................. 178 9.6.2 Port Control Register 7 (PCR7) ............................................................................ 179 9.6.3 Pin Functions ........................................................................................................ 179 Port 8.................................................................................................................................. 180 9.7.1 Port Data Register 8 (PDR8)................................................................................. 181 9.7.2 Port Control Register 8 (PCR8) ............................................................................ 181 9.7.3 Pin Functions ........................................................................................................ 182 Port 9.................................................................................................................................. 183 9.8.1 Port Data Register 9 (PDR9)................................................................................. 183 9.8.2 Port Control Register 9 (PCR9) ............................................................................ 184 9.8.3 Port Mode Register 9 (PMR9) .............................................................................. 184 9.8.4 Pin Functions ........................................................................................................ 185 Port A................................................................................................................................. 186 9.9.1 Port Data Register A (PDRA)............................................................................... 187
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9.10
9.11
9.12
9.13
9.14 9.15 9.16
9.9.2 Port Control Register A (PCRA) .......................................................................... 187 9.9.3 Pin Functions ........................................................................................................ 188 Port B ................................................................................................................................. 190 9.10.1 Port Data Register B (PDRB) ............................................................................... 190 9.10.2 Port Mode Register B (PMRB)............................................................................. 191 9.10.3 Pin Functions ........................................................................................................ 192 Port C ................................................................................................................................. 194 9.11.1 Port Data Register C (PDRC) ............................................................................... 194 9.11.2 Port Control Register C (PCRC)........................................................................... 195 9.11.3 Pin Functions ........................................................................................................ 195 Port E ................................................................................................................................. 196 9.12.1 Port Data Register E (PDRE)................................................................................ 196 9.12.2 Port Control Register E (PCRE) ........................................................................... 197 9.12.3 Port Mode Register E (PMRE) ............................................................................. 197 9.12.4 Pin Functions ........................................................................................................ 198 Port F ................................................................................................................................. 202 9.13.1 Port Data Register F (PDRF) ................................................................................ 202 9.13.2 Port Control Register F (PCRF)............................................................................ 203 9.13.3 Port Mode Register F (PMRF).............................................................................. 203 9.13.4 Pin Functions ........................................................................................................ 204 Input/Output Data Inversion .............................................................................................. 206 9.14.1 Serial Port Control Register, Serial Port Control Register 2 (SPCR, SPCR2)...... 206 Port Function Switch.......................................................................................................... 209 9.15.1 Port Function Control Register (PFCR)................................................................ 209 Usage Notes ....................................................................................................................... 210 9.16.1 How to Handle Unused Pin .................................................................................. 210 9.16.2 Input Characteristics Difference due to Pin Function ........................................... 210
Section 10 Realtime Clock (RTC)..................................................................... 211
10.1 Features.............................................................................................................................. 211 10.2 Input/Output Pin ................................................................................................................ 212 10.3 Register Descriptions ......................................................................................................... 212 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) ............. 213 10.3.2 Minute Data Register (RMINDR) ........................................................................ 214 10.3.3 Hour Data Register (RHRDR) .............................................................................. 215 10.3.4 Day-of-Week Data Register (RWKDR) ............................................................... 216 10.3.5 RTC Control Register 1 (RTCCR1) ..................................................................... 217 10.3.6 RTC Control Register 2 (RTCCR2) ..................................................................... 219 10.3.7 Clock Source Select Register (RTCCSR) ............................................................. 220 10.3.8 RTC Interrupt Flag Register (RTCFLG) .............................................................. 221
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10.4 Operation ........................................................................................................................... 222 10.4.1 Initial Settings of Registers after Power-On ......................................................... 222 10.4.2 Initial Setting Procedure ....................................................................................... 222 10.4.3 Data Reading Procedure ....................................................................................... 223 10.5 Interrupt Sources................................................................................................................ 224 10.6 Usage Notes ....................................................................................................................... 225 10.6.1 Note on Clock Count ............................................................................................ 225 10.6.2 Note when Using RTC Interrupts ......................................................................... 225
Section 11 Timer C ............................................................................................227
11.1 Features.............................................................................................................................. 227 11.2 Input/Output Pins ............................................................................................................... 228 11.3 Register Descriptions ......................................................................................................... 228 11.3.1 Timer Mode Register C (TMC) ............................................................................ 229 11.3.2 Timer Counter C (TCC)........................................................................................ 231 11.3.3 Timer Load Register C (TLC) .............................................................................. 231 11.3.4 Clock Halt Register 3 (CKSTPR3) ....................................................................... 231 11.4 Timer Operation................................................................................................................. 232 11.4.1 Interval Timer Operation ...................................................................................... 232 11.4.2 Auto-Reload Timer Operation .............................................................................. 233 11.4.3 Event Counter Operation ...................................................................................... 233 11.4.4 TCC Up/Down Control by the External Input Pin................................................ 233 11.5 Timer C Operation States................................................................................................... 234
Section 12 Timer F.............................................................................................235
12.1 Features.............................................................................................................................. 235 12.2 Input/Output Pins ............................................................................................................... 236 12.3 Register Descriptions ......................................................................................................... 237 12.3.1 Timer Counters FH and FL (TCFH, TCFL) ......................................................... 237 12.3.2 Output Compare Registers FH and FL (OCRFH, OCRFL) .................................. 238 12.3.3 Timer Control Register F (TCRF) ........................................................................ 239 12.3.4 Timer Control/Status Register F (TCSRF) ........................................................... 240 12.4 Operation ........................................................................................................................... 242 12.4.1 Timer F Operation ................................................................................................ 242 12.4.2 TCF Increment Timing ......................................................................................... 244 12.4.3 TMOFH/TMOFL Output Timing ......................................................................... 245 12.4.4 TCF Clear Timing................................................................................................. 245 12.4.5 Timer Overflow Flag (OVF) Set Timing .............................................................. 246 12.4.6 Compare Match Flag Set Timing.......................................................................... 246 12.5 Timer F Operating States ................................................................................................... 247
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12.6 Usage Notes ....................................................................................................................... 248 12.6.1 16-Bit Timer Mode ............................................................................................... 248 12.6.2 8-Bit Timer Mode ................................................................................................. 248 12.6.3 Flag Clearing ........................................................................................................ 249 12.6.4 Timer Counter (TCF) Read/Write ........................................................................ 251
Section 13 Timer G ........................................................................................... 253
13.1 Features.............................................................................................................................. 253 13.2 Input/Output Pins............................................................................................................... 255 13.3 Register Descriptions ......................................................................................................... 255 13.3.1 Timer Counter G (TCG) ....................................................................................... 255 13.3.2 Input Capture Register GF (ICRGF)..................................................................... 256 13.3.3 Input Capture Register GR (ICRGR).................................................................... 256 13.3.4 Timer Mode Register G (TMG)............................................................................ 256 13.3.5 Clock Halt Register 3 (CKSTPR3) ....................................................................... 259 13.4 Noise Canceller.................................................................................................................. 259 13.5 Operation ........................................................................................................................... 261 13.5.1 Timer G Functions................................................................................................ 261 13.5.2 Count Timing........................................................................................................ 262 13.5.3 Input Capture Input Timing .................................................................................. 262 13.5.4 Timing of Input Capture by Input Capture Input.................................................. 263 13.5.5 TCG Clear Timing ................................................................................................ 264 13.6 Timer G Operation Modes ................................................................................................. 265 13.7 Usage Notes ....................................................................................................................... 266 13.7.1 Internal Clock Switching and TCG Operation...................................................... 266 13.7.2 Notes on Port Mode Register Modification .......................................................... 267 13.8 Timer G Application Example........................................................................................... 270
Section 14 16-Bit Timer Pulse Unit (TPU) .......................................................271
14.1 Features.............................................................................................................................. 271 14.2 Input/Output Pins............................................................................................................... 273 14.3 Register Descriptions ......................................................................................................... 274 14.3.1 Timer Control Register (TCR).............................................................................. 275 14.3.2 Timer Mode Register (TMDR)............................................................................. 277 14.3.3 Timer I/O Control Register (TIOR) ...................................................................... 278 14.3.4 Timer Interrupt Enable Register (TIER)............................................................... 283 14.3.5 Timer Status Register (TSR)................................................................................. 284 14.3.6 Timer Counter (TCNT)......................................................................................... 285 14.3.7 Timer General Register (TGR) ............................................................................. 285 14.3.8 Timer Start Register (TSTR) ................................................................................ 286
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14.3.9 Timer Synchro Register (TSYR) .......................................................................... 287 14.4 Interface to CPU ................................................................................................................ 288 14.4.1 16-Bit Registers .................................................................................................... 288 14.4.2 8-Bit Registers ...................................................................................................... 288 14.5 Operation ........................................................................................................................... 290 14.5.1 Basic Functions..................................................................................................... 290 14.5.2 Synchronous Operation......................................................................................... 296 14.5.3 Operation with Cascaded Connection................................................................... 298 14.5.4 PWM Modes ......................................................................................................... 300 14.6 Interrupt Sources................................................................................................................ 305 14.7 Operation Timing............................................................................................................... 306 14.7.1 Input/Output Timing ............................................................................................. 306 14.7.2 Interrupt Signal Timing......................................................................................... 309 14.8 Usage Notes ....................................................................................................................... 311 14.8.1 Module Standby Function Setting......................................................................... 311 14.8.2 Input Clock Restrictions ....................................................................................... 311 14.8.3 Caution on Period Setting ..................................................................................... 312 14.8.4 Contention between TCNT Write and Clear Operation ....................................... 312 14.8.5 Contention between TCNT Write and Increment Operation ................................ 313 14.8.6 Contention between TGR Write and Compare Match .......................................... 314 14.8.7 Contention between TGR Read and Input Capture............................................... 315 14.8.8 Contention between TGR Write and Input Capture.............................................. 316 14.8.9 Contention between Overflow and Counter Clearing ........................................... 317 14.8.10 Contention between TCNT Write and Overflow .................................................. 318 14.8.11 Multiplexing of I/O Pins ....................................................................................... 318 14.8.12 Interrupts when Module Standby Function is Used .............................................. 318 14.8.13 Output Conditions for 0% Duty and 100% Duty .................................................. 318
Section 15 Asynchronous Event Counter (AEC)...............................................319
15.1 Features.............................................................................................................................. 319 15.2 Input/Output Pins ............................................................................................................... 320 15.3 Register Descriptions ......................................................................................................... 321 15.3.1 Event Counter PWM Compare Register (ECPWCR) ........................................... 321 15.3.2 Event Counter PWM Data Register (ECPWDR) .................................................. 322 15.3.3 Input Pin Edge Select Register (AEGSR) ............................................................. 323 15.3.4 Event Counter Control Register (ECCR) .............................................................. 324 15.3.5 Event Counter Control/Status Register (ECCSR) ................................................. 325 15.3.6 Event Counter H (ECH)........................................................................................ 327 15.3.7 Event Counter L (ECL)......................................................................................... 327 15.4 Operation ........................................................................................................................... 328
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15.4.1 16-Bit Counter Operation ..................................................................................... 328 15.4.2 8-Bit Counter Operation ....................................................................................... 329 15.4.3 IRQAEC Operation............................................................................................... 330 15.4.4 Event Counter PWM Operation............................................................................ 330 15.4.5 Operation of Clock Input Enable/Disable Function.............................................. 331 15.5 Operating States of Asynchronous Event Counter............................................................. 332 15.6 Usage Notes ....................................................................................................................... 333
Section 16 Watchdog Timer.............................................................................. 335
16.1 Features.............................................................................................................................. 335 16.2 Register Descriptions ......................................................................................................... 336 16.2.1 Timer Control/Status Register WD1 (TCSRWD1)............................................... 337 16.2.2 Timer Control/Status Register WD2 (TCSRWD2)............................................... 339 16.2.3 Timer Counter WD (TCWD)................................................................................ 340 16.2.4 Timer Mode Register WD (TMWD) .................................................................... 341 16.3 Operation ........................................................................................................................... 342 16.3.1 Watchdog Timer Mode......................................................................................... 342 16.3.2 Interval Timer Mode............................................................................................. 343 16.3.3 Timing of Overflow Flag (OVF) Setting .............................................................. 343 16.4 Interrupt ............................................................................................................................. 344 16.5 Usage Notes ....................................................................................................................... 344 16.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode................. 344 16.5.2 Module Standby Mode Control ............................................................................ 344 16.5.3 Writing to Timer Counter WD (TCWD) with the On-Chip Watchdog Timer Oscillator Selected .................................................................... 344
Section 17 Serial Communications Interface 3 (SCI3, IrDA)...........................345
17.1 Features.............................................................................................................................. 345 17.2 Input/Output Pins............................................................................................................... 351 17.3 Register Descriptions ......................................................................................................... 351 17.3.1 Receive Shift Register (RSR) ............................................................................... 352 17.3.2 Receive Data Register (RDR) ............................................................................... 352 17.3.3 Transmit Shift Register (TSR) .............................................................................. 352 17.3.4 Transmit Data Register (TDR).............................................................................. 352 17.3.5 Serial Mode Register (SMR) ................................................................................ 353 17.3.6 Serial Control Register (SCR) .............................................................................. 356 17.3.7 Serial Status Register (SSR) ................................................................................. 358 17.3.8 Bit Rate Register (BRR) ....................................................................................... 361 17.3.9 Serial Port Control Register (SPCR)..................................................................... 373 17.3.10 Serial Port Control Register 2 (SPCR2)................................................................ 375
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17.4
17.5
17.6
17.7
17.8 17.9
17.3.11 IrDA Control Register (IrCR) ............................................................................... 376 17.3.12 Serial Extended Mode Register (SEMR) .............................................................. 377 Operation in Asynchronous Mode ..................................................................................... 378 17.4.1 Clock..................................................................................................................... 379 17.4.2 SCI3 Initialization................................................................................................. 383 17.4.3 Data Transmission ................................................................................................ 384 17.4.4 Serial Data Reception ........................................................................................... 386 Operation in Clock Synchronous Mode............................................................................. 390 17.5.1 Clock..................................................................................................................... 390 17.5.2 SCI3 Initialization................................................................................................. 390 17.5.3 Serial Data Transmission ...................................................................................... 391 17.5.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 393 17.5.5 Simultaneous Serial Data Transmission and Reception........................................ 395 Multiprocessor Communication Function.......................................................................... 396 17.6.1 Multiprocessor Serial Data Transmission ............................................................. 398 17.6.2 Multiprocessor Serial Data Reception .................................................................. 399 IrDA Operation .................................................................................................................. 401 17.7.1 Transmission......................................................................................................... 402 17.7.2 Reception .............................................................................................................. 403 17.7.3 High-Level Pulse Width Selection........................................................................ 403 Interrupt Requests .............................................................................................................. 404 Usage Notes ....................................................................................................................... 407 17.9.1 Break Detection and Processing ........................................................................... 407 17.9.2 Mark State and Break Sending.............................................................................. 407 17.9.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) ......................................................................... 407 17.9.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................................................... 408 17.9.5 Note on Switching SCK3 Pin Function ................................................................ 409 17.9.6 Relation between Writing to TDR and Bit TDRE ................................................ 409 17.9.7 Relation between RDR Reading and bit RDRF .................................................... 410 17.9.8 Transmit and Receive Operations when Making State Transition........................ 411 17.9.9 Setting in Subactive or Subsleep Mode ................................................................ 411 17.9.10 Oscillator when Serial Communications Interface 3 is Used................................ 411
Section 18 Serial Communication Interface 4 (SCI4) .......................................413
18.1 Features.............................................................................................................................. 413 18.2 Input/Output Pins ............................................................................................................... 414 18.3 Register Descriptions ......................................................................................................... 415 18.3.1 Serial Control Register 4 (SCR4).......................................................................... 415
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18.3.2 Serial Control/Status Register 4 (SCSR4) ............................................................ 418 18.3.3 Transmit Data Register 4 (TDR4)......................................................................... 421 18.3.4 Receive Data Register 4 (RDR4) .......................................................................... 421 18.3.5 Shift Register 4 (SR4)........................................................................................... 421 18.4 Operation ........................................................................................................................... 422 18.4.1 Clock..................................................................................................................... 422 18.4.2 Data Transfer Format............................................................................................ 422 18.4.3 Data Transmission/Reception ............................................................................... 423 18.4.4 Data Transmission ................................................................................................ 424 18.4.5 Data Reception...................................................................................................... 426 18.4.6 Simultaneous Data Transmission and Reception.................................................. 428 18.5 Interrupt Sources................................................................................................................ 429 18.6 Usage Notes ....................................................................................................................... 430 18.6.1 Relationship between Writing to TDR4 and TDRE ............................................. 430 18.6.2 Receive Error Flag and Transmission................................................................... 430 18.6.3 Relationship between Reading RDR4 and RDRF ................................................ 430 18.6.4 SCK4 Output Waveform when Internal Clock of /2 is Selected......................... 431
Section 19 14-Bit PWM .................................................................................... 433
19.1 Features.............................................................................................................................. 433 19.2 Input/Output Pins............................................................................................................... 434 19.3 Register Descriptions ......................................................................................................... 434 19.3.1 PWM Control Register (PWCR) .......................................................................... 435 19.3.2 PWM Data Register (PWDR) ............................................................................... 436 19.4 Operation ........................................................................................................................... 436 19.4.1 Principle of Pulse-Division Type PWM ............................................................... 436 19.4.2 Setting for Pulse-Division Type PWM Operation ................................................ 437 19.4.3 Operation of Pulse-Division Type PWM.............................................................. 437 19.4.4 Setting for Standard PWM Operation................................................................... 438 19.4.5 PWM Operating States ......................................................................................... 439 19.5 Usage Notes ....................................................................................................................... 439 19.5.1 Timing of Writing to PWDR and Reflection in the PWM Waveform.................. 439
Section 20 A/D Converter ................................................................................. 441
20.1 Features.............................................................................................................................. 441 20.2 Input/Output Pins............................................................................................................... 443 20.3 Register Descriptions ......................................................................................................... 443 20.3.1 A/D Result Register (ADRR) ............................................................................... 444 20.3.2 A/D Mode Register (AMR) .................................................................................. 444 20.3.3 A/D Start Register (ADSR) .................................................................................. 446
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20.4 Operation ........................................................................................................................... 446 20.4.1 A/D Conversion .................................................................................................... 446 20.4.2 External Trigger Input Timing.............................................................................. 447 20.4.3 Operating States of A/D Converter ....................................................................... 447 20.5 Example of Use.................................................................................................................. 448 20.6 A/D Conversion Accuracy Definitions .............................................................................. 451 20.7 Usage Notes ....................................................................................................................... 453 20.7.1 Permissible Signal Source Impedance .................................................................. 453 20.7.2 Influences on Absolute Accuracy ......................................................................... 453 20.7.3 Other Usage Notes ................................................................................................ 454
Section 21 LCD Controller/Driver.....................................................................455
21.1 Features.............................................................................................................................. 455 21.2 Input/Output Pins ............................................................................................................... 457 21.3 Register Descriptions ......................................................................................................... 457 21.3.1 LCD Port Control Register (LPCR)...................................................................... 458 21.3.2 LCD Control Register (LCR)................................................................................ 460 21.3.3 LCD Control Register 2 (LCR2)........................................................................... 462 21.3.4 LCD Trimming Register (LTRMR)...................................................................... 463 21.3.5 BGR Control Register (BGRMR)......................................................................... 465 21.4 Operation ........................................................................................................................... 466 21.4.1 Settings up to LCD Display .................................................................................. 466 21.4.2 Relationship between LCD RAM and Display ..................................................... 468 21.4.3 3-V Constant-Voltage Power Supply Circuit........................................................ 473 21.4.4 Operation in Power-Down Modes ........................................................................ 474 21.4.5 Boosting LCD Drive Power Supply and Fine Adjustment ................................... 476 21.5 Usage Notes ....................................................................................................................... 477 21.5.1 Pin Handling when LCD Controller/Driver is not Used ....................................... 477 21.5.2 Pin Handling when 3-V Constant-Voltage Power Supply Circuit is not Used ..... 477
Section 22 I C Bus Interface 2 (IIC2) ................................................................479
22.1 Features.............................................................................................................................. 479 22.2 Input/Output Pins ............................................................................................................... 481 22.3 Register Descriptions ......................................................................................................... 482 2 22.3.1 I C Bus Control Register 1 (ICCR1) ..................................................................... 482 2 22.3.2 I C Bus Control Register 2 (ICCR2) ..................................................................... 485 2 22.3.3 I C Bus Mode Register (ICMR)............................................................................ 487 2 22.3.4 I C Bus Interrupt Enable Register (ICIER) ........................................................... 489 2 22.3.5 I C Bus Status Register (ICSR)............................................................................. 491 22.3.6 Slave Address Register (SAR) .............................................................................. 494
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2
22.4
22.5 22.6 22.7
22.3.7 I C Bus Transmit Data Register (ICDRT) ............................................................ 494 2 22.3.8 I C Bus Receive Data Register (ICDRR).............................................................. 494 2 22.3.9 I C Bus Shift Register (ICDRS)............................................................................ 494 Operation ........................................................................................................................... 495 2 22.4.1 I C Bus Format...................................................................................................... 495 22.4.2 Master Transmit Operation ................................................................................... 496 22.4.3 Master Receive Operation .................................................................................... 498 22.4.4 Slave Transmit Operation ..................................................................................... 500 22.4.5 Slave Receive Operation....................................................................................... 503 22.4.6 Clock Synchronous Serial Format ........................................................................ 504 22.4.7 Noise Canceller..................................................................................................... 507 22.4.8 Example of Use..................................................................................................... 507 Interrupt Request................................................................................................................ 512 Bit Synchronous Circuit..................................................................................................... 513 Usage Notes ....................................................................................................................... 514 22.7.1 Note on Issuing Stop Condition and Start (Re-Transmit) Condition .................... 514 2 22.7.2 Note on Setting WAIT Bit in I C Bus Mode Register (ICMR)............................. 514 22.7.3 Restriction on Transfer Rate Setting in Multimaster Operation ........................... 514 22.7.4 Restriction on the Use of Bit Manipulation Instructions for MST and TRS Setting in Multimaster Operation ................................................................. 515 22.7.5 Usage Note on Master Receive Mode................................................................... 515
2
Section 23 Power-On Reset Circuit................................................................... 517
23.1 Feature ............................................................................................................................... 517 23.2 Operation ........................................................................................................................... 518 23.2.1 Power-On Reset Circuit ........................................................................................ 518
Section 24 Address Break ................................................................................. 519
24.1 Register Descriptions ......................................................................................................... 520 24.1.1 Address Break Control Register 2 (ABRKCR2) .................................................. 520 24.1.2 Address Break Status Register 2 (ABRKSR2) ..................................................... 522 24.1.3 Break Address Registers 2 (BAR2E, BAR2H, BAR2L) ...................................... 522 24.1.4 Break Data Registers 2 (BDR2H, BDR2L) .......................................................... 522 24.2 Operation ........................................................................................................................... 523 24.3 Operating States of Address Break .................................................................................... 524
Section 25 List of Registers............................................................................... 525
25.1 Register Addresses (Address Order).................................................................................. 526 25.2 Register Bits....................................................................................................................... 533 25.3 Register States in Each Operating Mode ........................................................................... 540
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Section 26 Electrical Characteristics .................................................................547
26.1 Absolute Maximum Ratings for F-ZTAT Version............................................................. 547 26.2 Electrical Characteristics for F-ZTAT Version.................................................................. 548 26.2.1 Power Supply Voltage and Operating Range........................................................ 548 26.2.2 DC Characteristics ................................................................................................ 554 26.2.3 AC Characteristics ................................................................................................ 562 26.2.4 A/D Converter Characteristics .............................................................................. 568 26.2.5 LCD Characteristics.............................................................................................. 570 26.2.6 Power-On Reset Circuit Characteristics................................................................ 571 26.2.7 Watchdog Timer Characteristics........................................................................... 572 26.2.8 Flash Memory Characteristics .............................................................................. 573 26.3 Absolute Maximum Ratings for Masked ROM Version.................................................... 575 26.4 Electrical Characteristics for Masked ROM Version......................................................... 576 26.4.1 Power Supply Voltage and Operating Range........................................................ 576 26.4.2 DC Characteristics ................................................................................................ 580 26.4.3 AC Characteristics ................................................................................................ 588 26.4.4 A/D Converter Characteristics .............................................................................. 594 26.4.5 LCD Characteristics.............................................................................................. 596 26.4.6 Power-On Reset Circuit Characteristics................................................................ 597 26.4.7 Watchdog Timer Characteristics........................................................................... 597 26.5 Operation Timing............................................................................................................... 598 26.6 Output Load Circuit ........................................................................................................... 601 26.7 Recommended Resonators................................................................................................. 602 26.8 Usage Note......................................................................................................................... 602
Appendix
A.
..........................................................................................................603
B.
C. D.
Instruction Set .................................................................................................................... 603 A.1 Instruction List...................................................................................................... 603 A.2 Operation Code Map............................................................................................. 618 A.3 Number of Execution States ................................................................................. 621 A.4 Combinations of Instructions and Addressing Modes .......................................... 632 I/O Ports............................................................................................................................. 633 B.1 I/O Port Block Diagrams ...................................................................................... 633 B.2 Port States in Each Operating State ...................................................................... 661 Product Part No. Lineup..................................................................................................... 663 Package Dimensions .......................................................................................................... 664
Main Revisions and Additions in this Edition .....................................................665 Index ..........................................................................................................689
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Figures
Section 1 Overview Figure 1.1 Internal Block Diagram of H8/38099 Group................................................................. 3 Figure 1.2 Pin Assignment of H8/38099 Group (PLQP0100KB-A) .............................................. 4 Section 2 CPU Figure 2.1 Memory Map............................................................................................................... 13 Figure 2.2 CPU Registers ............................................................................................................. 14 Figure 2.3 Usage of General Registers ......................................................................................... 15 Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 16 Figure 2.5 General Register Data Formats (1) .............................................................................. 18 Figure 2.5 General Register Data Formats (2) .............................................................................. 19 Figure 2.6 Memory Data Formats................................................................................................. 20 Figure 2.7 Instruction Formats...................................................................................................... 31 Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 35 Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 38 Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 39 Figure 2.11 CPU Operating States................................................................................................ 40 Figure 2.12 State Transitions ........................................................................................................ 41 Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address ........................................................................................................... 42 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Exception Handling Reset Exception Handling Sequence ........................................................................... 50 Interrupt Sources and their Numbers........................................................................... 51 Stack Status after Exception Handling ........................................................................ 52 Operation when Odd Address is Set in SP .................................................................. 53 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag Clearing Procedure ..................................................................................................... 56 Interrupt Controller Block Diagram of Interrupt Controller ........................................................................ 59 Flowchart of Procedure Up to Interrupt Acceptance ................................................... 79 Interrupt Exception Handling Sequence...................................................................... 80 Contention between Interrupt Generation and Disabling ............................................ 82 Clock Pulse Generator Block Diagram of Clock Pulse Generator ................................................................... 85 Typical Connection to Crystal Resonator.................................................................... 88 Typical Connection to Ceramic Resonator.................................................................. 89
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Figure 5.4 Example of External Clock Input ................................................................................ 89 Figure 5.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator................................ 91 Figure 5.6 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 92 Figure 5.7 Pin Connection when not Using Subclock .................................................................. 92 Figure 5.8 Pin Connection when Inputting External Clock .......................................................... 93 Figure 5.9 Example of Crystal and Ceramic Resonator Arrangement.......................................... 95 Figure 5.10 Negative Resistance Measurement and Circuit Modification Suggestions ............... 96 Figure 5.11 Example of Incorrect Board Design .......................................................................... 97 Figure 5.12 Oscillation Stabilization Wait Time .......................................................................... 98 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Section 7 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Power-Down Modes Mode Transition Diagram ......................................................................................... 111 Standby Mode Transition and Pin States................................................................... 124 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode ......................................................................................................... 126 ROM Flash Memory Block Configuration.......................................................................... 128 Sample Flowchart of Programming/Erasing in User Program Mode........................ 137 Address Map of Overlaid RAM Area ....................................................................... 139 Program/Program-Verify Flowchart ......................................................................... 141 Erase/Erase-Verify Flowchart ................................................................................... 144 Module Standby Mode Setting when RAM Emulation is not Used.......................... 148
Section 9 I/O Ports Figure 9.1 Port 1 Pin Configuration............................................................................................ 151 Figure 9.2 Port 3 Pin Configuration............................................................................................ 160 Figure 9.3 Port 4 Pin Configuration............................................................................................ 166 Figure 9.4 Port 5 Pin Configuration............................................................................................ 170 Figure 9.5 Port 6 Pin Configuration............................................................................................ 174 Figure 9.6 Port 7 Pin Configuration............................................................................................ 178 Figure 9.7 Port 8 Pin Configuration............................................................................................ 180 Figure 9.8 Port 9 Pin Configuration............................................................................................ 183 Figure 9.9 Port A Pin Configuration........................................................................................... 186 Figure 9.10 Port B Pin Configuration......................................................................................... 190 Figure 9.11 Port C Pin Configuration......................................................................................... 194 Figure 9.12 Port E Pin Configuration ......................................................................................... 196 Figure 9.13 Port F Pin Configuration ......................................................................................... 202 Figure 9.14 Input/Output Data Inversion Function..................................................................... 206 Section 10 Realtime Clock (RTC) Figure 10.1 Block Diagram of RTC ........................................................................................... 211
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Figure 10.2 Definition of Time Expression ................................................................................ 218 Figure 10.3 Initial Setting Procedure .......................................................................................... 222 Figure 10.4 Example: Reading of Inaccurate Time Data............................................................ 223 Section 11 Timer C Figure 11.1 Block Diagram of Timer C...................................................................................... 227 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Timer F Block Diagram of Timer F ...................................................................................... 236 Count Timing for Internal Clock Operation ............................................................ 244 Count Timing for External Event Operation ........................................................... 244 TMOFH/TMOFL Output Timing............................................................................ 245 TCF Clear Timing ................................................................................................... 245 Compare Match Flag Set Timing ............................................................................ 246 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid... 251
Timer G Block Diagram of Timer G...................................................................................... 254 Noise Canceller Block Diagram .............................................................................. 259 Noise Canceller Timing (Example) ......................................................................... 260 Input Capture Input Timing (without Noise Cancellation Function)....................... 262 Input Capture Input Timing (with Noise Cancellation Function)............................ 263 Timing of Input Capture by Input Capture Input..................................................... 263 TCG Clear Timing................................................................................................... 264 Port Mode Register Manipulation and Interrupt Enable Flag Clearing Procedure ................................................................................................. 269 Figure 13.9 Timer G Application Example ................................................................................ 270 Section 14 16-Bit Timer Pulse Unit (TPU) Figure 14.1 Block Diagram of TPU............................................................................................ 273 Figure 14.2 16-Bit Register Access Operation [CPU TCNT (16 Bits)]................................. 288 Figure 14.3 8-Bit Register Access Operation [CPU TCR (Upper 8 Bits)] ............................ 288 Figure 14.4 8-Bit Register Access Operation [CPU TMDR (Lower 8 Bits)] ........................ 289 Figure 14.5 Example of Counter Operation Setting Procedure .................................................. 290 Figure 14.6 Free-Running Counter Operation ............................................................................ 291 Figure 14.7 Periodic Counter Operation..................................................................................... 292 Figure 14.8 Example of Setting Procedure for Waveform Output by Compare Match.............. 292 Figure 14.9 Example of 0 Output/1 Output Operation ............................................................... 293 Figure 14.10 Example of Toggle Output Operation ................................................................... 293 Figure 14.11 Example of Setting Procedure for Input Capture Operation.................................. 294 Figure 14.12 Example of Input Capture Operation..................................................................... 295 Figure 14.13 Example of Synchronous Operation Setting Procedure ........................................ 296
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Figure 14.14 Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Figure 14.25 Figure 14.26 Figure 14.27 Figure 14.28 Figure 14.29 Figure 14.30 Figure 14.31 Figure 14.32 Figure 14.33 Figure 14.34 Figure 14.35 Figure 14.36 Figure 14.37 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4
Example of Synchronous Operation...................................................................... 297 Setting Procedure for Operation with Cascaded Operation................................... 298 Example of Operation with Cascaded Connection................................................ 299 Example of PWM Mode Setting Procedure .......................................................... 301 Example of PWM Mode Operation (1) ................................................................. 302 Example of PWM Mode Operation (2) ................................................................. 303 Example of PWM Mode Operation (3) ................................................................. 304 Count Timing in Internal Clock Operation............................................................ 306 Count Timing in External Clock Operation .......................................................... 306 Output Compare Output Timing ........................................................................... 307 Input Capture Input Signal Timing........................................................................ 308 Counter Clear Timing (Compare Match) .............................................................. 308 Counter Clear Timing (Input Capture) .................................................................. 309 TGI Interrupt Timing (Compare Match) ............................................................... 309 TGI Interrupt Timing (Input Capture) ................................................................... 310 TCIV Interrupt Setting Timing.............................................................................. 310 Timing for Status Flag Clearing by CPU .............................................................. 311 Contention between TCNT Write and Clear Operation ........................................ 312 Contention between TCNT Write and Increment Operation................................. 313 Contention between TGR Write and Compare Match........................................... 314 Contention between TGR Read and Input Capture ............................................... 315 Contention between TGR Write and Input Capture .............................................. 316 Contention between Overflow and Counter Clearing............................................ 317 Contention between TCNT Write and Overflow................................................... 318
Asynchronous Event Counter (AEC) Block Diagram of Asynchronous Event Counter .................................................... 320 Software Procedure when Using ECH and ECL as 16-Bit Event Counter.............. 328 Software Procedure when Using ECH and ECL as 8-Bit Event Counters .............. 329 Event Counter Operation Waveform....................................................................... 330 Example of Clock Control Operation...................................................................... 331 Watchdog Timer Block Diagram of Watchdog Timer ........................................................................ 336 Example of Watchdog Timer Operation ................................................................. 342 Interval Timer Mode Operation............................................................................... 343 Timing of OVF Flag Setting ................................................................................... 343
Section 17 Serial Communications Interface 3 (SCI3, IrDA) Figure 17.1 (1) Block Diagram of SCI3_1 ................................................................................. 348 Figure 17.1 (2) Block Diagram of SCI3_2 ................................................................................. 349 Figure 17.1 (3) Block Diagram of SCI3_3 ................................................................................. 350
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Figure 17.2 Data Format in Asynchronous Communication ...................................................... 378 Figure 17.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)............. 379 Figure 17.4 Sample SCI3 Initialization Flowchart...................................................................... 383 Figure 17.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 384 Figure 17.6 Sample Serial Transmission Flowchart (Asynchronous Mode)............................... 385 Figure 17.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 387 Figure 17.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1) ...................... 388 Figure 17.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) ...................... 389 Figure 17.9 Data Format in Clock Synchronous Communications ............................................. 390 Figure 17.10 Example of SCI3 Operation in Transmission in Clock Synchronous Mode.......... 391 Figure 17.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode)..................... 392 Figure 17.12 Example of SCI3 Reception Operation in Clock Synchronous Mode ................... 393 Figure 17.13 Sample Serial Reception Flowchart (Clock Synchronous Mode).......................... 394 Figure 17.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clock Synchronous Mode)................................................................................... 395 Figure 17.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ...................................................................... 397 Figure 17.16 Sample Multiprocessor Serial Transmission Flowchart......................................... 398 Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (1) ........................................ 399 Figure 17.18 Example of SCI3 Operation in Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 400 Figure 17.19 IrDA Block Diagram ............................................................................................. 401 Figure 17.20 IrDA Transmission and Reception ........................................................................ 402 Figure 17.21 (a) RDRF Setting and RXI3 Interrupt ................................................................... 406 Figure 17.21 (b) TDRE Setting and TXI3 Interrupt ................................................................... 406 Figure 17.21 (c) TEND Setting and TEI3 Interrupt.................................................................... 406 Figure 17.22 Receive Data Sampling Timing in Asynchronous Mode ...................................... 408 Figure 17.23 Relation between RDR Read Timing and Data ..................................................... 410 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Serial Communication Interface 4 (SCI4) Block Diagram of SCI4 ........................................................................................... 414 Data Transfer Format .............................................................................................. 422 Flowchart Example of SCI4 Initialization............................................................... 423 Flowchart Example of Data Transmission .............................................................. 424 Transmit Operation Example................................................................................... 425 Flowchart Example of Data Reception.................................................................... 426 Receive Operation Example .................................................................................... 427 Flowchart Example of Simultaneous Transmission and Reception ........................ 428
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Figure 18.9 Relationship between Reading RDR4 and RDRF ................................................... 431 Figure 18.10 Transfer Format when Internal Clock of /2 is Selected ....................................... 431 Section 19 14-Bit PWM Figure 19.1 Block Diagram of 14-Bit PWM .............................................................................. 433 Figure 19.2 Example of Waveform Produced by Pulse-Division Type PWM (Division by 4) ........................................................................................................ 436 Figure 19.3 Waveform Output by PWM .................................................................................... 437 Section 20 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 Figure 20.6 Figure 20.7 Figure 20.8 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Figure 21.7 Figure 21.8 Figure 21.9 A/D Converter Block Diagram of A/D Converter ........................................................................... 442 External Trigger Input Timing ................................................................................ 447 Example of A/D Conversion Operation .................................................................. 449 Flowchart of Procedure for Using A/D Converter (Polling by Software) ............... 450 Flowchart of Procedure for Using A/D Converter (Interrupts Used) ...................... 450 A/D Conversion Accuracy Definitions (1) .............................................................. 452 A/D Conversion Accuracy Definitions (2) .............................................................. 452 Example of Analog Input Circuit ............................................................................ 453
LCD Controller/Driver Block Diagram of LCD Controller/Driver .............................................................. 456 Handling of LCD Drive Power Supply when Using 1/2 Duty ................................ 466 LCD RAM Map (1/4 Duty)..................................................................................... 468 LCD RAM Map (1/3 Duty)..................................................................................... 469 LCD RAM Map (1/2 Duty)..................................................................................... 469 LCD RAM Map (Static Mode) ............................................................................... 470 Output Waveforms for Each Duty Cycle (A Waveform) ........................................ 471 Output Waveforms for Each Duty Cycle (B Waveform) ........................................ 472 Capacitance Connection when Using 3-V Constant-Voltage Power Supply Circuit.............................................................................................. 474 Figure 21.10 Connection of External Split Resistor ................................................................... 476 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Figure 22.6 Figure 22.7 Figure 22.8 Figure 22.9 I2C Bus Interface 2 (IIC2) Block Diagram of I2C Bus Interface 2..................................................................... 480 External Circuit Connections of I/O Pins ................................................................ 481 I2C Bus Formats ...................................................................................................... 495 I2C Bus Timing........................................................................................................ 495 Master Transmit Mode Operation Timing (1) ......................................................... 497 Master Transmit Mode Operation Timing (2) ......................................................... 497 Master Receive Mode Operation Timing (1) .......................................................... 499 Master Receive Mode Operation Timing (2) .......................................................... 500 Slave Transmit Mode Operation Timing (1) ........................................................... 501
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Figure 22.10 Figure 22.11 Figure 22.12 Figure 22.13 Figure 22.14 Figure 22.15 Figure 22.16 Figure 22.17 Figure 22.18 Figure 22.19 Figure 22.20 Figure 22.21
Slave Transmit Mode Operation Timing (2) ......................................................... 502 Slave Receive Mode Operation Timing (1)........................................................... 503 Slave Receive Mode Operation Timing (2)........................................................... 504 Clock Synchronous Serial Transfer Format .......................................................... 504 Transmit Mode Operation Timing......................................................................... 505 Receive Mode Operation Timing .......................................................................... 506 Block Diagram of Noise Canceller........................................................................ 507 Sample Flowchart for Master Transmit Mode....................................................... 508 Sample Flowchart for Master Receive Mode ........................................................ 509 Sample Flowchart for Slave Transmit Mode......................................................... 510 Sample Flowchart for Slave Receive Mode .......................................................... 511 Timing of Bit Synchronous Circuit ....................................................................... 513
Section 23 Power-On Reset Circuit Figure 23.1 Power-On Reset Circuit........................................................................................... 517 Figure 23.2 Power-On Reset Circuit Operation Timing ............................................................. 518 Section 24 Figure 24.1 Figure 24.2 Figure 24.2 Section 26 Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 Figure 26.5 Figure 26.6 Address Break Block Diagram of Address Break............................................................................ 519 Address Break Interrupt Operation Example (1)..................................................... 523 Address Break Interrupt Operation Example (2)..................................................... 524
Electrical Characteristics Power Supply Voltage and Oscillation Frequency Range (1) ................................. 548 Power Supply Voltage and Oscillation Frequency Range (2) ................................. 549 Power Supply Voltage and Operating Frequency Range (1)................................... 550 Power Supply Voltage and Operating Frequency Range (2)................................... 551 Power Supply Voltage and Operating Frequency Range (3)................................... 552 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (1).................................................................................................... 553 Figure 26.7 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2).................................................................................................... 553 Figure 26.8 Power Supply Voltage and Oscillation Frequency Range (1) ................................. 576 Figure 26.9 Power Supply Voltage and Oscillation Frequency Range (2) ................................. 576 Figure 26.10 Power Supply Voltage and Operating Frequency Range (1)................................. 577 Figure 26.11 Power Supply Voltage and Operating Frequency Range (2)................................. 578 Figure 26.12 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (1).................................................................................................. 578 Figure 26.13 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2).................................................................................................. 579 Figure 26.14 Clock Input Timing ............................................................................................... 598 Figure 26.15 RES Low Width Timing........................................................................................ 598
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Figure 26.16 Figure 26.17 Figure 26.18 Figure 26.19 Figure 26.20 Figure 26.21 Figure 26.22 Figure 26.23
Input Timing.......................................................................................................... 598 SCK3 Input Clock Timing .................................................................................... 599 SCI3 Input/Output Timing in Clock Synchronous Mode...................................... 599 Clock Input Timing for TCLKA to TCLKC Pins ................................................. 600 I2C Bus Interface Input/Output Timing ................................................................. 600 UD Pin Minimum Transition Width Timing ......................................................... 600 Output Load Condition.......................................................................................... 601 Recommended Resonators .................................................................................... 602
Appendix Figure B.1 (a) Port 1 Block Diagram (P16) (F-ZTATTM Version) ............................................. 633 Figure B.1 (b) Port 1 Block Diagram (P16) (Masked ROM Version)........................................ 634 Figure B.1 (c) Port 1 Block Diagram (P15 to P12)..................................................................... 634 Figure B.1 (d) Port 1 Block Diagram (P11, P10) ....................................................................... 635 Figure B.2 (a) Port 3 Block Diagram (P37) (F-ZTATTM Version) ............................................. 636 Figure B.2 (b) Port 3 Block Diagram (P37) (Masked ROM Version)........................................ 636 Figure B.2 (c) Port 3 Block Diagram (P36) (F-ZTATTM Version) ............................................. 637 Figure B.2 (d) Port 3 Block Diagram (P36) (Masked ROM Version)........................................ 637 Figure B.2 (e) Port 3 Block Diagram (P32)................................................................................ 638 Figure B.2 (f) Port 3 Block Diagram (P31) ................................................................................ 639 Figure B.2 (g) Port 3 Block Diagram (P30)................................................................................ 640 Figure B.3 (a) Port 4 Block Diagram (P42)................................................................................ 641 Figure B.3 (b) Port 4 Block Diagram (P41)................................................................................ 642 Figure B.3 (c) Port 4 Block Diagram (P40)................................................................................ 643 Figure B.4 Port 5 Block Diagram ............................................................................................... 644 Figure B.5 Port 6 Block Diagram ............................................................................................... 645 Figure B.6 Port 7 Block Diagram ............................................................................................... 645 Figure B.7 Port 8 Block Diagram ............................................................................................... 646 Figure B.8 (a) Port 9 Block Diagram (P93)................................................................................ 646 Figure B.8 (b) Port 9 Block Diagram (P92)................................................................................ 647 Figure B.8 (c) Port 9 Block Diagram (P91, P90)........................................................................ 648 Figure B.9 Port A Block Diagram .............................................................................................. 648 Figure B.10 (a) Port B Block Diagram (PB7 to PB3)................................................................. 649 Figure B.10 (b) Port B Block Diagram (PB2 to PB0) ................................................................ 650 Figure B.11 Port C Block Diagram (PC7 to PC0) ...................................................................... 651 Figure B.12 (a) Port E Block Diagram (PE7) ............................................................................. 651 Figure B.12 (b) Port E Block Diagram (PE6)............................................................................. 652 Figure B.12 (c) Port E Block Diagram (PE5) ............................................................................. 652 Figure B.12 (d) Port E Block Diagram (PE4)............................................................................. 653 Figure B.12 (e) Port E Block Diagram (PE3) ............................................................................. 654 Figure B.12 (f) Port E Block Diagram (PE2) ............................................................................. 655
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Figure B.12 (g) Port E Block Diagram (PE1)............................................................................. 655 Figure B.12 (h) Port E Block Diagram (PE0)............................................................................. 656 Figure B.13 (a) Port F Block Diagram (PF3).............................................................................. 657 Figure B.13 (b) Port F Block Diagram (PF2) ............................................................................. 658 Figure B.13 (c) Port F Block Diagram (PF1).............................................................................. 659 Figure B.13 (d) Port F Block Diagram (PF0) ............................................................................. 660 Figure D.1 Package Dimensions (PLQP0100KB-A).................................................................. 664
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Tables
Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 21 Table 2.2 Data Transfer Instructions....................................................................................... 22 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 23 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 24 Table 2.4 Logic Operations Instructions................................................................................. 25 Table 2.5 Shift Instructions..................................................................................................... 25 Table 2.6 Bit Manipulation Instructions ................................................................................. 26 Table 2.7 Branch Instructions ................................................................................................. 28 Table 2.8 System Control Instructions.................................................................................... 29 Table 2.9 Block Data Transfer Instructions ............................................................................ 30 Table 2.10 Addressing Modes .................................................................................................. 32 Table 2.11 Absolute Address Access Ranges ........................................................................... 34 Table 2.12 Effective Address Calculation (1)........................................................................... 36 Table 2.12 Effective Address Calculation (2)........................................................................... 37 Section 3 Exception Handling Table 3.1 Exception Sources and Vector Address .................................................................. 48 Table 3.2 Interrupt Sources that Cause a Reset....................................................................... 49 Table 3.3 Conditions under which Interrupt Request Flag is Set to 1..................................... 55 Section 4 Interrupt Controller Table 4.1 Pin Configuration.................................................................................................... 60 Table 4.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities................................. 74 Table 4.3 Interrupt Control States........................................................................................... 77 Table 4.4 Interrupt Response Times (States) .......................................................................... 81 Section 5 Clock Pulse Generator Table 5.1 Selection of the System Clock Oscillator or On-Chip Oscillator for the System Clock .................................................................................................... 90 Section 6 Power-Down Modes Table 6.1 Operating Frequency and Wait Time.................................................................... 106 Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling................................................................................................. 112 Table 6.3 Internal State in Each Operating Mode................................................................. 115
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Section 7 ROM Table 7.1 Setting Programming Modes ................................................................................ 134 Table 7.2 Boot Mode Operation ........................................................................................... 136 Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ........................................................................................ 137 Table 7.4 Reprogram Data Computation Table .................................................................... 142 Table 7.5 Additional-Program Data Computation Table ...................................................... 142 Table 7.6 Programming Time ............................................................................................... 142 Table 7.7 Flash Memory Operating States............................................................................ 147 Section 10 Realtime Clock (RTC) Table 10.1 Pin Configuration.................................................................................................. 212 Table 10.2 Interrupt Sources................................................................................................... 224 Section 11 Timer C Table 11.1 Pin Configuration.................................................................................................. 228 Table 11.2 Timer C Operation States ..................................................................................... 234 Section 12 Timer F Table 12.1 Pin Configuration.................................................................................................. 236 Table 12.2 Timer F Operating States ...................................................................................... 247 Section 13 Timer G Table 13.1 Pin Configuration.................................................................................................. 255 Table 13.2 Timer G Operation Modes .................................................................................... 265 Table 13.3 Internal Clock Switching and TCG Operation...................................................... 266 Table 13.4 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching, and Conditions for Their Occurrence.................................. 268 Table 13.5 Input Capture Input Signal Input Edges Due to Noise Canceller Function Switching, and Conditions for Their Occurrence ................................................. 268 Section 14 16-Bit Timer Pulse Unit (TPU) Table 14.1 TPU Functions ...................................................................................................... 272 Table 14.2 Pin Configuration.................................................................................................. 273 Table 14.3 CCLR1 and CCLR0 (Channels 1 and 2)............................................................... 276 Table 14.4 TPSC2 to TPSC0 (Channel 1) .............................................................................. 276 Table 14.5 TPSC2 to TPSC0 (Channel 2) .............................................................................. 277 Table 14.6 MD1 to MD0 ........................................................................................................ 278 Table 14.7 TIOR_1 (Channel 1) ............................................................................................. 279 Table 14.8 TIOR_2 (Channel 2) ............................................................................................. 280 Table 14.9 TIOR_1 (Channel 1) ............................................................................................. 281 Table 14.10 TIOR_2 (Channel 2) ......................................................................................... 282 Table 14.11 Counter Combination in Operation with Cascaded Connection ....................... 298
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Table 14.12 Table 14.13
PWM Output Registers and Output Pins .......................................................... 301 TPU Interrupts .................................................................................................. 305
Section 15 Asynchronous Event Counter (AEC) Table 15.1 Pin Configuration.................................................................................................. 320 Table 15.2 Examples of Event Counter PWM Operation....................................................... 331 Table 15.3 Operating States of Asynchronous Event Counter................................................ 332 Table 15.4 Maximum Clock Frequency ................................................................................. 333 Section 17 Serial Communications Interface 3 (SCI3, IrDA) Table 17.1 SCI3 Channel Configuration................................................................................. 347 Table 17.2 Pin Configuration.................................................................................................. 351 Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (1)....................................................................................................... 362 Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (2)....................................................................................................... 363 Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (3)....................................................................................................... 364 Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (4)....................................................................................................... 365 Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (1)....................................................................................................... 366 Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (2)....................................................................................................... 367 Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (3)....................................................................................................... 368 Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (4)....................................................................................................... 369 Table 17.5 Correspondence between n and Clock .................................................................. 369 Table 17.6 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 370 Table 17.7 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1) ................... 371 Table 17.7 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2) ................... 372 Table 17.8 Correspondence between n and Clock .................................................................. 373 Table 17.9 Data Transfer Formats (Asynchronous Mode) ..................................................... 380 Table 17.10 SMR Settings and Corresponding Data Transfer Formats ................................ 381 Table 17.11 SMR and SCR Settings and Clock Source Selection ........................................ 382 Table 17.12 SSR Status Flags and Receive Data Handling .................................................. 387 Table 17.13 IrCKS2 to IrCKS0 Bit Settings......................................................................... 403 Table 17.14 SCI3 Interrupt Requests .................................................................................... 404 Table 17.15 Transmit/Receive Interrupts.............................................................................. 405
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Section 18 Serial Communication Interface 4 (SCI4) Table 18.1 Pin Configuration.................................................................................................. 414 Table 18.2 Prescaler Division Ratio and Transfer Clock Cycle (Internal Clock) ................... 420 Table 18.3 SCI4 Interrupt Sources.......................................................................................... 429 Section 19 14-Bit PWM Table 19.1 Pin Configuration.................................................................................................. 434 Table 19.2 Relationship between PWCR, PWDR and Output Waveform.............................. 438 Table 19.3 PWM Operating States ......................................................................................... 439 Section 20 A/D Converter Table 20.1 Pin Configuration.................................................................................................. 443 Table 20.2 Operating States of A/D Converter....................................................................... 447 Section 21 LCD Controller/Driver Table 21.1 Pin Configuration.................................................................................................. 457 Table 21.2 Duty Cycle and Common Function Selection....................................................... 458 Table 21.3 Segment Driver Selection ..................................................................................... 459 Table 21.4 Frame Frequency Selection................................................................................... 461 Table 21.5 Output Levels........................................................................................................ 473 Table 21.6 Power-Down Modes and Display Operation ........................................................ 475 Section 22 I2C Bus Interface 2 (IIC2) Table 22.1 Pin Configuration.................................................................................................. 481 Table 22.2 Transfer Rate ........................................................................................................ 484 Table 22.3 Interrupt Requests ................................................................................................. 512 Table 22.4 Time for Monitoring SCL..................................................................................... 513 Section 24 Address Break Table 24.1 Access and Data Bus Used ................................................................................... 521 Table 24.2 Operating States of Address Break ....................................................................... 524 Section 26 Electrical Characteristics Table 26.1 Absolute Maximum Ratings ................................................................................. 547 Table 26.2 DC Characteristics ................................................................................................ 554 Table 26.3 Control Signal Timing .......................................................................................... 562 Table 26.4 Serial Interface Timing ......................................................................................... 566 Table 26.5 I2C Bus Interface Timing ...................................................................................... 567 Table 26.6 A/D Converter Characteristics.............................................................................. 568 Table 26.7 LCD Characteristics.............................................................................................. 570 Table 26.8 Power-On Reset Circuit Characteristics ............................................................... 571 Table 26.9 Watchdog Timer Characteristics........................................................................... 572 Table 26.10 Flash Memory Characteristics .......................................................................... 573
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Table 26.11 Table 26.12 Table 26.13 Table 26.14 Table 26.15 Table 26.16 Table 26.17 Table 26.18 Table 26.19 Appendix Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5
Absolute Maximum Ratings ............................................................................. 575 DC Characteristics ............................................................................................ 580 Control Signal Timing ...................................................................................... 588 Serial Interface Timing ..................................................................................... 592 I2C Bus Interface Timing .................................................................................. 593 A/D Converter Characteristics .......................................................................... 594 LCD Characteristics.......................................................................................... 596 Power-On Reset Circuit Characteristics............................................................ 597 Watchdog Timer Characteristics....................................................................... 597 Instruction Set ....................................................................................................... 605 Operation Code Map (1) ....................................................................................... 618 Operation Code Map (2) ....................................................................................... 619 Operation Code Map (3) ....................................................................................... 620 Number of Cycles in Each Instruction .................................................................. 622 Number of Cycles in Each Instruction .................................................................. 623 Combinations of Instructions and Addressing Modes .......................................... 632
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Section 1 Overview
Section 1 Overview
1.1 Features
* High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions * Various peripheral functions RTC (can be used as a free-running counter) Asynchronous event counter (AEC) LCD controller/driver Timer C Timer F Timer G 16-bit timer pulse unit (TPU) 14-bit PWM Watchdog timer SCI (Asynchronous or clock synchronous serial communications interface) I C bus interface (conforms to the I C bus interface format that is advocated by Philips Electronics) 10-bit A/D converter
2 2
Rev. 2.00 Jul. 04, 2007 Page 1 of 692 REJ09B0309-0200
Section 1 Overview
* On-chip memory
Product Classification Flash memory version (F-ZTATTM version) Masked ROM version H8/38099F H8/38099 H8/38098 Model HD64F38099 HD64338099 HD64338098 ROM 128 Kbytes 128 Kbytes 96 Kbytes RAM 4 Kbytes 4 Kbytes 2 Kbytes
Note: F-ZTAT
TM
is a trademark of Renesas Technology Corp.
* General I/O ports I/O pins: 75 I/O pins, including 4 large current ports (IOL = 15 mA, @VOL = 1.0 V) Input-only pins: 8 input pins * Supports various power-down states * Compact package
Package P-LQFP-100 Code Body Size Pin Pitch 0.5 mm Remarks PLQP100KB-A 14 x 14 mm
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Section 1 Overview
1.2
Internal Block Diagram
X1 X2 OSC1 OSC2
Subclock pulse generator System clock pulse generator On-chip oscillator for system clock
H8/300H CPU
Vcc AVcc Vss Vss/AVss RES TEST/ADTRG NMI *2 P80/SEG25 P81/SEG26 P82/SEG27 P83/SEG28 P84/SEG29 P85/SEG30 P86/SEG31 P87/SEG32 PC0/SEG33 PC1/SEG34 PC2/SEG35 PC3/SEG36 PC4/SEG37 PC5/SEG38 PC6/SEG39 PC7/SEG40 P90/PWM1 P91/PWM2 P92/IRQ4/PWM3 P93/PWM4
P10/AEVH P11/AEVL P12/TIOCA1/TCLKA P13/TIOCB1/TCLKB P14/TIOCA2/TCLKC P15/TIOCB2 P16/SCK4 *1*2
ROM
Port 1
RAM
Port 8
Power-on reset circuit
Watchdog timer
P30/SCK32/TMOW/CLKOUT P31/RXD32/SDA P32/TXD32/SCL 12 P36/SI4 * * P37/SO4 *1*2 IRQAEC P40/SCK31/TMIF P41/RXD31/IrRXD/TMOFL P42/TXD31/IrTXD/TMOFH P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 V1 V2 V3 C1 C2 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16 P70/SEG17 P71/SEG18 P72/SEG19 P73/SEG20 P74/SEG21 P75/SEG22 P76/SEG23 P77/SEG24
Port 3
Realtime Clock
Timer pulse unit
Asynchronous event counter
Port 4
Timer C
Timer F
Timer G
Port 9
Port C
Port 5
14-bit PWM1
14-bit PWM2
PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 PB0/AN0/IRQ0 PB1/AN1/IRQ1 PB2/AN2/IRQ3 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PE0/SCK33(/IRQ3) PE1/RXD33 PE2/TXD33 PE3(/SCK32/IRQ1) PE4(/RXD32) PE5(/TXD32) PE6/UD PE7/TMIC(/IRQ0) PF0/TMIG PF1(/SCK31/IRQ4) PF2(/RXD31/IrRXD) PF3(/TXD31/IrTXD)
14-bit PWM3
LCD power supply
14-bit PWM4
Port B
LCD controller/ driver
10-bit A/D converter
I2C bus interface
Port 6
SCI3_1/IrDA
Port E
SCI3_2
SCI3_3
Port 7
SCI4*1
Address break
: Large current port (15 mA)
Notes: 1. The SCI4 pins, such as SCK4, SI4, and SO4, are supported only by the F-ZTAT version. 2. The SCK4, SI4, SO4, and NMI pins are not available when the E8 or on-chip emulator debugger is used. These pins are not available as ports.
Figure 1.1 Internal Block Diagram of H8/38099 Group
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Port F
Port A
Section 1 Overview
1.3
Pin Assignment
AVcc PB0/AN0/IRQ0 PB1/AN1/IRQ1 PB2/AN2/IRQ3 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 Vss/AVss TEST/ADTRG PE7/TMIC(/IRQ0) PE6/UD PE5(/TXD32) PE4(/RXD32) PE3(/SCK32/IRQ1) PE2/TXD33 PE1/RXD33 PE0/SCK33(/IRQ3) PF3(/TXD31/IrTXD) PF2(/RXD31/IrRXD) PF1(/SCK31/IRQ4) PF0/TMIG P42/TXD31/IrTXD/TMOFH P41/RXD31/IrRXD/TMOFL
54 53 52 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 51 20 21 22 23 9 10 11 12 13 14 15 16 17 18
Figure 1.2 Pin Assignment of H8/38099 Group (PLQP0100KB-A)
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P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16 P70/SEG17 P71/SEG18 P72/SEG19 P73/SEG20 P74/SEG21 P75/SEG22 P76/SEG23 P77/SEG24 P80/SEG25
19
1
2
3
4
5
6
7
8
24 25
IRQAEC P10/AEVH P11/AEVL P12/TIOCA1/TCLKA P13/TIOCB1/TCLKB P14/TIOCA2/TCLKC P15/TIOCB2 NMI X1 X2 RES OSC1 Vss OSC2 Vcc P16/SCK4 P37/SO4 P36/SI4 P32/TXD32/SCL P31/RXD32/SDA P30/SCK32/TMOW/CLKOUT P90/PWM1 P91/PWM2 P92/IRQ4/PWM3 P93/PWM4
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
50 49 48 47 46 45 44 43 42 41 40 39
PLQP0100KB-A (Top view)
38 37 36 35 34 33 32 31 30 29 28 27 26
100
P40/SCK31/TMIF C2 C1 V3 V2 V1 (also used for 3V booster) PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 PC7/SEG40 PC6/SEG39 PC5/SEG38 PC4/SEG37 PC3/SEG36 PC2/SEG35 PC1/SEG34 PC0/SEG33 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26
Section 1 Overview
1.4
Table 1.1
Type
Pin Functions
Pin Functions
Symbol Vcc Vss AVcc Pin No. 90 88, 66 (= AVss) 75 I/O Input Input Input Functions Power supply pin. Connect this pin to the system power supply. Ground pins. Connect these pins to the system power supply (0 V). Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. Ground pin for the A/D converter. Connect this pin to the system power supply (0 V). Power supply pins for the LCD controller/driver. Capacitance pins for stepping up the LCD drive power supply. These pins connect crystal or ceramic resonator for the system clock, or can be used to input an external clock. See section 5, Clock Pulse Generator, for a connection. X1 X2 84 85 Input These pins connect a 32.768- or 38.4-kHz crystal resonator for the subclock. See section 5, Clock Pulse Output Generator, for a connection.
Power supply pins
AVss V1 to V3 C1 C2 Clock pins OSC1 OSC2
66 (= Vss) 45 to 47 48 49 87 89
Input Input Input Input Input Output
CLKOUT 96
Output Pin for supplying the system clock to external devices
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Section 1 Overview Type System control Symbol RES Pin No. 86 I/O Input Functions Reset pin. The power-on reset circuit is incorporated. When externally driven low, the chip is reset. Test pin. Also used as the ADTRG pin. When this pin is not used as the ADTRG pin, users cannot use this pin. Connect this pin to Vss. When this pin is used as the ADTRG pin, see section 20.4.2, External Trigger Input Timing. NMI interrupt request pin. Non-maskable interrupt request input pin. IRQ0 (IRQ0) IRQ1 (IRQ1) IRQ3 (IRQ3) IRQ4 (IRQ4) IRQAEC 74 64 73 60 72 57 99 54 76 Input Interrupt input pin for the asynchronous event counter. This pin enables the asynchronous event input. This pin turns on/off the on-chip oscillator for the system clock during a reset. WKP0 to WKP7 1 to 8 Input Wakeup interrupt request input pins. Sensing of rising or falling edges selectable. Input Input Input Input External interrupt request input pins. Sensing of rising or falling edges selectable.
TEST
65
Input
Interrupt pins
NMI
83
Input
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Section 1 Overview Type 16-bit timer pulse unit (TPU) Symbol TIOCA1 TIOCB1 TIOCA2 TIOCB2 TCLKA TCLKB TCLKC Timer C TMIC UD Pin No. 79 80 81 82 79 80 81 64 63 I/O I/O I/O I/O I/O Input Input Input Input Input Event input pin for the timer C counter (TCC). Selects whether the TCC counts up or down. TCC counts up when the UD pin input is low, and counts down when the input is high. Event input pin for input to the timer F counter. Functions Pin for the TGR1A input capture input or output compare output, or PWM output. Pin for the TGR1B input capture input or output compare output, or PWM output. Pin for the TGR2A input capture input or output compare output, or PWM output. Pin for the TGR2B input capture input or output compare output, or PWM output. External clock input pins.
Timer F
TMIF TMOFL TMOFH
50 51 52 53 78 77 96
Input
Output Output pin for waveforms generated by the timer FL output compare function. Output Output pin for waveforms generated by the timer FH output compare function. Input Input Input Output Divided clock output pin for the RTC. Pin for the timer G input capture input Event input pins for input to the asynchronous event counter.
Timer G
TMIG
AsynchAEVL ronous event counter AEVH (AEC) RTC TMOW
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Section 1 Overview Type 14-bit PWM Symbol PWM1 PWM2 PWM3 PWM4 Serial SCK4 communications interface 4 SI4 (SCI4) (F-ZTAT version only) SO4 Serial communications interface 3 (SCI3) SCK31 (SCK31)
RXD31/IrRXD
Pin No. 97 98 99 100 91
I/O
Functions
Output Output pins for waveforms generated by the 14-bit PWM in PWM channels 1, 2, 3, and 4. Output Output Output I/O Transfer clock pin for SCI4 data transmission/reception. When the E8 or on-chip emulator debugger is used, this pin is not available. SCI4 data input pin. When the E8 or on-chip emulator debugger is used, this pin is not available.
93 92 50 54 51
Input
Output SCI4 data output pin. When the E8 or on-chip emulator debugger is used, this pin is not available. I/O SCI3_1 clock I/O pins.
Input
(RXD31/IrRXD) 55 TXD31/IrTXD
SCI3_1 data input pins or data input pins for the IrDA format.
52
(TXD31/IrTXD) 56
Output SCI3_1 data output pins or data output pins for the IrDA format. I/O SCI3_2 clock I/O pins.
SCK32 (SCK32) RXD32 (RXD32) TXD32 (TXD32) SCK33 RXD33 TXD33
96 60 95 61 94 62 57 58 59
Input
SCI3_2 data input pins.
Output SCI3_2 data output pins.
I/O Input
SCI3_3 clock I/O pin. SCI3_3 data input pin.
Output SCI3_3 data output pin.
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Section 1 Overview Type A/D converter Symbol AN0 to AN7 ADTRG I C bus interface 2 (IIC2)
2
Pin No. 74 to 67 65 95
I/O Input Input I/O
Functions Analog data input pins for the A/D converter. External trigger input pin for the A/D converter. IIC data I/O pin.
SDA
SCL LCD controller/ driver COM1 to COM4 SEG1 to SEG8 SEG9 to SEG16 SEG17 to SEG24 SEG25 to SEG32 SEG33 to SEG40 I/O ports P10 to P16 P30 to P32, P36, P37 P40 to P42 P50 to P57 P60 to P67
94 41 to 44
I/O
IIC clock I/O pin.
Output LCD common output pins.
1 to 8 9 to 16 17 to 24 25 to 32 33 to 40 77 to 82, 91 96 to 92 50 to 52 1 to 8 9 to 16
Output LCD segment output pins. Output Output Output Output I/O I/O I/O I/O I/O 7-bit I/O pins. Input or output can be designated for each bit by means of the port control register 1 (PCR1). 5-bit I/O pins. Input or output can be designated for each bit by means of the port control register 3 (PCR3). 3-bit I/O pins. Input or output can be designated for each bit by means of the port control register 4 (PCR4). 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 5 (PCR5). 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 6 (PCR6).
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Section 1 Overview Type I/O ports Symbol P70 to P77 P80 to P87 P90 to P93 PA0 to PA3 PB0 to PB7 PC0 to PC7 PE0 to PE7 PF0 to PF3 Pin No. 17 to 24 25 to 32 97 to 100 41 to 44 74 to 67 33 to 40 57 to 64 53 to 56 I/O I/O I/O I/O I/O Input I/O I/O I/O Functions 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 7 (PCR7). 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register 8 (PCR8). 4-bit I/O pins. Input or output can be designated for each bit by means of the port control register 9 (PCR9). 4-bit I/O pins. Input or output can be designated for each bit by means of the port control register A (PCRA). 8-bit input-only pins 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register C (PCRC). 8-bit I/O pins. Input or output can be designated for each bit by means of the port control register E (PCRE). 4-bit I/O pins. Input or output can be designated for each bit by means of the port control register F (PCRF).
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Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H can handle a 16-Mbyte linear address space and is ideal for realtime control. * Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added. * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers, or eight 32-bit registers * Sixty-two basic instructions 8/16/32-bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte linear address space * High-speed operation All frequently-used instructions execute in two or four states 8/16/32-bit register-register add/subtract : 2 state 8 x 8-bit register-register multiply 16 / 8-bit register-register divide 16 x 16-bit register-register multiply 32 / 16-bit register-register divide : 14 states : 14 states : 22 states : 22 states
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Section 2 CPU
* Two types of CPU operating modes Normal mode Advanced mode Note: Normal mode cannot be used in this LSI. * Power-down state Transition to power-down state by SLEEP instruction
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Section 2 CPU
2.1
Address Space and Memory Map
The address space of this LSI is 16 Mbytes, which includes the program area and the data area. Figure 2.1 shows the memory map.
HD64F38099 (Flash memory version) H'000000 H'0000DF H'0000E0 Interrupt vector H'000000 H'0000DF H'0000E0 HD64338099 (Masked ROM version) Interrupt vector H'000000 H'0000DF H'0000E0 HD64338098 (Masked ROM version) Interrupt vector
On-chip ROM (128 Kbytes)
On-chip ROM (128 Kbytes) H'017FFF H'018000
On-chip ROM (96 Kbytes)
H'01FFFF H'020000 Not used H'FFCF7F H'FFCF80 H'FFD37F H'FFD380 H'FFEFDF H'FFEFE0 Internal I/O registers (1) H'FFF09F H'FFF0A0 H'FFF35F H'FFF360 H'FFF373 H'FFF374 H'FFF37F H'FFF380 Not used LCDRAM (20 bytes) Not used On-chip RAM (2) (3 Kbytes) H'FFFF7F H'FFFF80 Internal I/O registers (2) H'FFFFFF
H'01FFFF H'020000 Not used Not used On-chip RAM (1) (1 Kbyte) Not used H'FFEFDF H'FFEFE0 Internal I/O registers (1) H'FFF09F H'FFF0A0 H'FFF35F H'FFF360 H'FFF373 H'FFF374 H'FFF37F H'FFF380 Not used LCDRAM (20 bytes) Not used On-chip RAM (2) (3 Kbytes) H'FFFF7F H'FFFF80 Internal I/O registers (2) H'FFFFFF H'FFFFFF H'FFF09F H'FFF0A0 H'FFF35F H'FFF360 H'FFF373 H'FFF374 H'FFF77F H'FFF780 H'FFFF7F H'FFFF80 Internal I/O registers (2) H'FFCF7F H'FFCF80 H'FFD37F H'FFD380 On-chip RAM (1) (1 Kbyte) Not used H'FFEFDF H'FFEFE0 Internal I/O registers (1) Not used LCDRAM (20 bytes) Not used On-chip RAM (2 Kbytes)
Figure 2.1 Memory Map
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Section 2 CPU
2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
General Registers (ERn)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR)
23 PC 0
76543210
CCR I UI H U N Z V C
[Legend]
SP: PC: CCR: I: UI: Stack pointer Program counter Condition-code register Interrupt mask bit User bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag
Figure 2.2 CPU Registers
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Section 2 CPU
2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. The usage of each register can be selected independently.
* Address registers * 32-bit registers * 16-bit registers * 8-bit registers
E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H)
Figure 2.3 Usage of General Registers
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Section 2 CPU
General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between the stack pointer and the stack area.
Empty area SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
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Section 2 CPU
Bit 7
Bit Name I
Initial Value 1
R/W R/W
Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
6
UI
Undefined R/W
User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag Stores the value of the most significant bit of data as a sign bit.
2
Z
Undefined R/W
Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
1
V
Undefined R/W
Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
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Section 2 CPU
2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type
1-bit data
General Register
RnH
Data Format
7 0 Don't care 7 0 76 54 32 10
1-bit data
RnL
Don't care
76 54 32 10
7 4-bit BCD data RnH Upper
43 Lower
0 Don't care
7 4-bit BCD data RnL Don't care Upper
43 Lower
0
7 Byte data RnH MSB
0 Don't care LSB 7 0 LSB
Byte data
RnL
Don't care MSB
Figure 2.5 General Register Data Formats (1)
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Section 2 CPU
Data Type Word data
General Register Rn
Data Format
15
0
Word data
En
15 0
MSB
LSB
MSB
LSB 16 15 0
Longword data
ERn
31
MSB
LSB
[Legend]
ERn: General register ER En: Rn: General register E General register R
RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit
Figure 2.5 General Register Data Formats (2)
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Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 (SP) is used as an address register to access the stack area, the operand size should be word or longword.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Format
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M+1
MSB LSB
Longword data
Address 2N Address 2N+1 Address 2N+2 Address 2N+3
MSB
LSB
Figure 2.6 Memory Data Formats
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Section 2 CPU
2.4
2.4.1
Instruction Set
Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined in table 2.1. Table 2.1
Symbol Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x /
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement)
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Section 2 CPU
Symbol :3/:8/:16/:24 Note: *
Description 3-, 8-, 16-, or 24-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
Table 2.2
Instruction MOV
Data Transfer Instructions
Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) Rd Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.3
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU
B
B/W/L
L B
B/W
MULXS
B/W
DIVXU
B/W
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.3
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.4
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement (logical complement) of general register contents.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Note:
*
Refers to the operand size. B: Byte W: Word L: Longword
Table 2.5
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: *
Shift Instructions
Size* B/W/L B/W/L B/W/L B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry flag.
Refers to the operand size. B: Byte W: Word L: Longword
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Section 2 CPU
Table 2.6
Instruction BSET
Bit Manipulation Instructions
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
BXOR
B
BIXOR
B
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Section 2 CPU
Instruction BLD
Size* B
Function ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BILD
B
BST
B
BIST
B
Note:
*
Refers to the operand size. B: Byte
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Section 2 CPU
Table 2.7
Instruction Bcc*
Branch Instructions
Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1
JMP BSR JSR RTS Note: *

Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
Bcc is the general name for conditional branch instructions.
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Section 2 CPU
Table 2.8
Instruction RTE SLEEP LDC
System Control Instructions
Size* B/W Function Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. CCR #IMM CCR Logically ANDs the CCR with immediate data. CCR #IMM CCR Logically ORs the CCR with immediate data. CCR #IMM CCR Logically XORs the CCR with immediate data. PC + 2 PC Only increments the program counter.
STC
B/W
ANDC ORC XORC NOP Note: *
B B B
Refers to the operand size. B: Byte W: Word
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Section 2 CPU
Table 2.9
Instruction EEPMOV.B
Block Data Transfer Instructions
Size Function if R4L 0 then Repeat @ER5+ @ER6+, R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+, R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
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Section 2 CPU
2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. (1) Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). (4) Condition Field
Specifies the branching condition of Bcc instructions.
(1) Operation field only op (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. NOP, RTS, etc.
(3) Operation field, register fields, and effective address extension op EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8 rn rm MOV.B @(d:16, Rn), Rm
Figure 2.7 Instruction Formats
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Section 2 CPU
2.5
2.5.1
Addressing Modes and Effective Address Calculation
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.10 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:24,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
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Section 2 CPU
(1)
Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
* Register indirect with post-increment@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. * Register indirect with pre-decrement@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. (5) Absolute Address@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space.
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Section 2 CPU
Table 2.11 shows the access ranges of absolute addresses. Table 2.11 Absolute Address Access Ranges
Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Access Range H'FFFF00 to H'FFFFFF (16776960 to 16777215) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32767, 16744448 to 16777215) H'000000 to H'FFFFFF (0 to 16777215)
(6)
Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. (7) Program-Counter Relative@(d:8, PC) or @(d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number.
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Section 2 CPU
(8)
Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed in words, generating a 16-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF). Note that the first part of the address range is also the exception vector area.
Specified by @aa:8 Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
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Section 2 CPU
2.5.2
Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. Table 2.12 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31
General register contents
Register indirect(@ERn)
0
23
0
op 3
r
Register indirect with displacement @(d:16,ERn) or @(d:24,ERn)
31
General register contents
0 23 0
op
r
disp 31
Sign extension
0 disp
4
Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+
31
General register contents
0
23
0
op
r 31
1, 2, or 4
*Register indirect with pre-decrement @-ERn
0
General register contents
23
0
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
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Section 2 CPU
Table 2.12 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8 op abs
23 H'FFFF
87
0
@aa:16 op abs
23
16 15
0
Sign extension
@aa:24 op abs 23 0
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:16,PC) @(d:8,PC)^
23
PC contents
0
op
disp
23
Sign extension
0 disp 23 0
8
Memory indirect @@aa:8
23 op abs H'0000 15
87 abs
0
0
Memory contents
23
16 15 H'00
0
[Legend] r, rm,rn : op : disp : IMM : abs :
Register field Operation field Displacement Immediate data Absolute address
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Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock () or a subclock (SUB). The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle T1 state or SUB T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal Internal data bus (write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
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Section 2 CPU
2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 25.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module.
Bus cycle T1 state or SUB T2 state T3 state
Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access)
Address
Read data
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. For the program halt state, there are sleep (high-speed or medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes. For details on exception handling, refer to section 3, Exception Handling.
CPU state
Reset state The CPU is initialized Program execution state Active (high-speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock
Active (medium-speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock
Program halt state A state in which the CPU operation is stopped to reduce power consumption
Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode
Exception-handling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operating States
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Power-down modes
Section 2 CPU
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Interrupt source
Exceptionhandling complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.12 State Transitions
2.8
2.8.1
Usage Notes
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4 or R4L, which starts from the address indicated by ER5, to the address indicated by ER6. Set R4 or R4L and ER6 so that the end address of the destination address (value of ER6 + R4 or ER6 + R4L) does not exceed H'00FFFFFF (the value of ER6 must not change from H'00FFFFFF to H'01000000 during execution).
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Section 2 CPU
2.8.3
Bit-Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, because this may rewrite data of a bit other than the bit to be manipulated. (1) Bit manipulation for two registers assigned to the same address
Example 1: Bit manipulation for the timer load register and timer counter Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register.
Read Count clock Timer counter
Reload Write Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address
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Section 2 CPU
Example 2: When the BSET instruction is executed for port 5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below. * Prior to executing BSET instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BSET instruction executed BSET #0, @PDR5:8 The BSET instruction is executed for port 5.
* After executing BSET instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 0 P56 Input High level 0 1 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output High level 1 1
* Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
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Section 2 CPU
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction. As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. * Prior to executing BSET instruction MOV.B MOV.B MOV.B H'80, R0L R0L, @RAM0 R0L, @PDR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0
The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output Low level 1 0 0
* BSET instruction executed BSET #0, @RAM0:8 The BSET instruction is executed designating the PDR5 work area (RAM0).
* After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0
The work area (RAM0) value is written to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output High level 1 1 1
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Section 2 CPU
(2)
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. * Prior to executing BCLR instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BCLR instruction executed BCLR #0, @PCR5:8 The BCLR instruction is executed for PCR5.
* After executing BCLR instruction
P57 Input/output Pin state PCR5 PDR5 Output Low level 1 1 P56 Output High level 1 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Input High level 0 0
* Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F. 2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PDR5.
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Section 2 CPU
* Prior to executing BCLR instruction MOV.B MOV.B MOV.B H'3F, R0L R0L, @RAM0 R0L, @PCR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0
The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output Low level 1 0 1
* BCLR instruction executed BCLR #0, @RAM0:8 The BCLR instructions executed for the PCR5 work area (RAM0). * After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0
The work area (RAM0) value is written to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output High level 0 0 0
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Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset or interrupts. * Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin. * Interrupts External interrupts other than NMI and internal interrupts other than address break are masked by the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued.
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Section 3 Exception Handling
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.1 Exception Sources and Vector Address
Exception Sources Vector Number 0 1, 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 to 55 Vector Address H'000000 to H'000003 H'000004 to H'00000B H'00000C to H'00000F H'000010 to H'000013 H'000014 to H'000017 H'000018 to H'00001B H'00001C to H'00001F H'000020 to H'000023 H'000024 to H'000027 H'000028 to H'00002B H'00002C to H'00002F H'000030 to H'000033 H'000034 to H'000037 H'000038 to H'00003B H'00003C to H'00003F H'000040 to H'000043 H'000044 to H'000047 H'000048 to H'00004B H'00004C to H'0000DF Low Priority High
Source Origin
RES pin/Watchdog Reset timer External interrupt Address break External interrupts Reserved for system use NMI Reserved for system use Break conditions satisfied IRQ0 IRQ1 IRQAEC IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Internal interrupts* Note: *
For details on the vector table of internal interrupts, see section 4.5, Interrupt Exception Handling Vector Table.
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Section 3 Exception Handling
3.2
Reset
A reset has the highest exception priority. Table 3.2 shows the three sources that cause a reset. Table 3.2
RES pin Power-on reset circuit
Interrupt Sources that Cause a Reset
Description Low-level input Rising of the power-supply voltage (Vcc) For details, see section 23, Power-On Reset Circuit.
Origin of Interrupt Source
Watchdog timer
Counter overflow For details, see section 16, Watchdog Timer.
3.2.1
Reset Exception Handling
When a reset is generated, all processing halts and this LSI enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. To ensure that this LSI be reset, the RES pin has to be held low for the oscillation stabilization time of the system clock oscillator either after power-on or when the system clock oscillator is halted. If the system clock oscillator is functioning, the RES pin has to be held low for the number of the tREL state as is specified by the electrical characteristics. When a reset source has been generated, this LSI starts reset exception handling as follows. 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized and the I bit in CCR is set to 1. 2. The reset exception handling vector address (H'000000 to H'000003) is read and transferred to the PC, and then program execution starts from the address indicated by the PC. The sequence of the reset exception handling caused by the RES pin is shown in figure 3.1.
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Section 3 Exception Handling
Vector fetch
Internal processing
Prefetch of first program instruction
RES
Internal address bus
(1)
(3)
(5)
Internal read signal
Internal write signal Internal data bus (16 bits)
(2)
(4)
(6)
(1), (3) (2), (4) (5) (6)
Reset exception handling vector address (1) = H'000000, (3) = H'000002 Start address (contents of reset exception handling vector address) Start address Initial program instruction
Figure 3.1 Reset Exception Handling Sequence 3.2.2 Interrupt Immediately after Reset
Immediately after a reset, if an interrupt is accepted before the stack pointer (SP) is initialized, PC and CCR will not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.L #xx: 32, SP).
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Section 3 Exception Handling
3.3
Interrupts
The interrupt sources include 14 external interrupts (NMI, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, and WKP7 to WKP0) and 28 internal interrupts (for the flash memory version) or 27 internal interrupts (for the masked ROM version) from on-chip peripheral modules. Figure 3.2 shows the interrupt sources and their numbers. The on-chip peripheral modules which require interrupt sources are the watchdog timer (WDT), address break, realtime clock (RTC), 16-bit timer pulse unit (TPU), asynchronous event counter (AEC), timer C, timer F, timer G, serial communication interface (SCI), and A/D converter. Interrupt vector addresses are allocated to individual sources. NMI is an interrupt with the highest priority and accepted at all times. Interrupts are controlled by the interrupt controller. The interrupt controller sets interrupts other than NMI to three levels of priorities in order to control multiple interrupts. The interrupt priority registers A to F (IPRA to IPRF) of the interrupt controller set the interrupt priorities. For details on interrupts, see section 4, Interrupt Controller.
NMI (1) IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC (5) WKP0 to WKP7 (8) WDT*1 (1) Address break (1) Realtime clock (8) Asynchronous event counter (1) 16-bit timer pulse unit (6) Timer C (1) Timer F (2) Timer G (1) SCI3 (3) SCI4*2 (1) A/D converter (1) SLEEP instruction execution (1) IIC bus (1)
External interrupts
Interrupts
Internal interrupts
Notes: ( ) indicates the source number. 1. When the WDT is used as an interval timer, an interrupt request is generated each time the counter overflows. 2. Available only for the F-ZTAT version.
Figure 3.2 Interrupt Sources and their Numbers
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Section 3 Exception Handling
3.4
Stack Status after Exception Handling
Figures 3.3 shows the stack after completion of interrupt exception handling.
SP - 4 SP - 3 SP - 2 SP - 1 SP (ER7) Stack area
SP (ER7) SP + 1 SP + 2 SP + 3 SP + 4
CCR PCE PCH PCL Even address
Prior to start of interrupt exception handling
PC and CCR saved to stack
After completion of interrupt exception handling
[Legend] Bits 23 to 16 of program counter (PC) PC E: Bits 15 to 8 of program counter (PC) PCH: Bits 7 to 0 of program counter (PC) PCL : Condition code register CCR: Stack pointer SP: Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored in word or longword units, starting from an even-numbered address.
Figure 3.3 Stack Status after Exception Handling
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Section 3 Exception Handling
3.5
3.5.1
Usage Notes
Notes on Stack Area Use
When word data or longword data is accessed in this LSI, the least significant bit of the address is regarded as 0. The stack must always be accessed in word units or longword units, and the stack pointer (SP: ER7) should never indicate an odd address. Use PUSH.W Rn (MOV.W Rn, @-SP) or PUSH.L ERn (MOV.L ERn, @-SP) to save register values. To restore register values, use POP.W Rn (MOV.W @SP+, Rn) or POP.L ERn (MOV.L @SP+, ERn). Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.4.
SP
CCR PC E PCH PC L
SP
R1L PCE PCH PCL
H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF
SP
BSR instruction SP set to H'FFFEFF [Legend] PC E : PC H: PC L : R1L: SP:
MOV. B R1L, @-ER7 Contents of CCR are lost
Stack accessed beyond SP
Bits 23 to 16 of program counter (PC) Bits 15 to 8 of program counter (PC) Bits 7 to 0 of program counter (PC) General register R1L Stack pointer
Figure 3.4 Operation when Odd Address is Set in SP
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Section 3 Exception Handling
3.5.2
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins and when the value of the ECPWME bit in AEGSR is rewritten to switch between selection and nonselection of IRQAEC, the following points should be observed. When a pin function is switched by rewriting a port mode register that controls an external interrupt pin (IRQ4, IRQ3, IRQ1, IRQ0, or WKP7 to WKP0), the interrupt request flag is set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching the pin function. When the value of the ECPWME bit in AEGSR that sets selection or non-selection of IRQAEC is rewritten, the interrupt request flag may be set to 1, even if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM output for the AEC). Therefore, be sure to clear the interrupt request flag to 0 after switching the pin function. Table 3.3 shows the conditions under which interrupt request flags are set to 1.
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Section 3 Exception Handling
Table 3.3
Conditions under which Interrupt Request Flag is Set to 1
Conditions When the IRQ4 bit in PMR9 or PMRF is changed from 0 to 1 while the IRQ4 pin is low and the IEG4 bit in IEGR is 0. When the IRQ4 bit in PMR9 or PMRF is changed from 1 to 0 while the IRQ4 pin is low and the IEG4 bit in IEGR is 1. IRRI3 When the IRQ3 bit in PMRB or PMRE is changed from 0 to 1 while the IRQ3 pin is low and the IEG3 bit in IEGR is 0. When the IRQ3 bit in PMRB or PMRE is changed from 1 to 0 while the IRQ3 pin is low and the IEG3 bit in IEGR is 1. IRREC2 When an edge as designated by the AIEGS1 and AIEGS0 bits in AEGSR is detected because the values of the IRQAEC pin and of IECPWM at switching are different (e.g., when the rising edge has been selected and the ECPWME bit in AEGSR is changed from 1 to 0 while the IRQAEC pin is low and IECPWM is 1). When the IRQ1 bit in PMRB or PMRE is changed from 0 to 1 while the IRQ1 pin is low and the IEG1 bit in IEGR is 0. When the IRQ1 bit in PMRB or PMRE is changed from 1 to 0 while the IRQ1 pin is low and the IEG1 bit in IEGR is 1. IRRI0 When the IRQ0 bit in PMRB or PMRE is changed from 0 to 1 while the IRQ0 pin is low and the IEG0 bit in IEGR is 0. When the IRQ0 bit in PMRB or PMRE is changed from 1 to 0 while the IRQ0 pin is low and the IEG0 bit in IEGR is 1.
Interrupt Request Flags Set to 1 IRR1 IRRI4
IRRI1
IWPR
IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
When the WKP7 bit in PMR5 is changed from 0 to 1 while the WKP7 pin is low. When the WKP6 bit in PMR5 is changed from 0 to 1 while the WKP6 pin is low. When the WKP5 bit in PMR5 is changed from 0 to 1 while the WKP5 pin is low. When the WKP4 bit in PMR5 is changed from 0 to 1 while the WKP4 pin is low. When the WKP3 bit in PMR5 is changed from 0 to 1 while the WKP3 pin is low. When the WKP2 bit in PMR5 is changed from 0 to 1 while the WKP2 pin is low. When the WKP1 bit in PMR5 is changed from 0 to 1 while the WKP1 pin is low. When the WKP0 bit in PMR5 is changed from 0 to 1 while the WKP0 pin is low.
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Section 3 Exception Handling
Figure 3.5 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. This procedure also applies to AEGSR setting. When switching a pin function, mask the interrupt before setting the bit in the port mode register (or AEGSR). After accessing the port mode register (or AEGSR), execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag to 0 is executed immediately after the port mode register (or AEGSR) access without executing an instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.2 are not satisfied. However, the procedure in figure 3.5 is recommended because IECPWM is an internal signal and determining its value is complicated.
Interrupts masked. (Another possibility is to disable the relevant interrupt in the interrupt enable register 1.)
I bit in CCR 1
Set port mode register (or AEGSR) bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register (or AEGSR) bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0
I bit in CCR 0
Interrupt mask cleared
Figure 3.5 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag Clearing Procedure
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Section 3 Exception Handling
3.5.3
Method for Clearing Interrupt Request Flags
Use the recommended method given below when clearing the flags in interrupt request registers (IRR1, IRR2, and IWPR). (1) Recommended method
Use a single instruction to clear flags. The bit manipulation instruction and byte-size data transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 in IRR1) are given below. BCLR #1, @IRR1:8
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101) (2) Example of a malfunction
When flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1 (bit 1 in IRR1). MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time AND.B #B'11111101,R1L ..... Here, IRRI0 = 1 MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0 In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B instruction is executing. The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1, IRRI0 is also cleared.
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Section 3 Exception Handling
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Section 4 Interrupt Controller
Section 4 Interrupt Controller
4.1 Features
This LSI includes an interrupt controller, which has the following features. * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Three mask levels can be set for each module for all interrupts except an NMI and address break. * Interrupts can be enabled or disabled in three levels by the INTM1 and INTM0 bits in the interrupt mask register (INTM). * Fourteen external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising or falling edge sensing can be selected for NMI. Rising or falling edge sensing can be selected for IRQ0, IRQ1, IRQ3, IRQ4, and WKP0 to WKP7. Rising, falling, or both edge sensing can be selected for IRQAEC. A block diagram of the interrupt controller is shown in figure 4.1.
NMI/IRQ/ WKP input
External interrupt input
Interrupt request Vector number CCR ............
IENR1 Internal interrupt source TPU, SCI, etc.
Priority determination
I
INTM
IPR [Legend] IENR1: IPR: CCR: INTM: IRQ enable register 1 Interrupt priority register Condition code register Interrupt mask register
Figure 4.1 Block Diagram of Interrupt Controller
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Section 4 Interrupt Controller
4.2
Input/Output Pins
Table 4.1 shows the pin configuration of the interrupt controller. Table 4.1
Pin Name NMI IRQAEC IRQ4 IRQ3 IRQ1 IRQ0 WKP7 to WKP0
Pin Configuration
I/O Input Input Input Input Input Input Input Maskable external interrupt pins Accepted at a rising or falling edge Function Nonmaskable external interrupt pin Rising or falling edge can be selected Maskable external interrupt pin Rising, falling, or both edges can be selected Maskable external interrupt pins Rising or falling edge can be selected
4.3
Register Descriptions
The interrupt controller has the following registers. * Interrupt edge select register (IEGR) * Wakeup edge select register (WEGR) * Interrupt enable register 1 (IENR1) * Interrupt enable register 2 (IENR2) * Interrupt request register 1 (IRR1) * Interrupt request register 2 (IRR2) * Wakeup interrupt request register (IWPR) * Interrupt priority register A (IPRA) * Interrupt priority register B (IPRB) * Interrupt priority register C (IPRC) * Interrupt priority register D (IPRD) * Interrupt priority register E (IPRE) * Interrupt priority register F (IPRF) * Interrupt mask register (INTM)
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Section 4 Interrupt Controller
4.3.1
Interrupt Edge Select Register (IEGR)
IEGR selects the sense of an edge that generates interrupt requests of the NMI, TMIF, ADTRG, IRQ4, IRQ3, IRQ1, and IRQ0 pins.
Bit 7 Bit Name NMIEG Initial Value 0 R/W R/W Descriptions NMI Edge Select 0: Detects a falling edge of the NMI pin input 1: Detects a rising edge of the NMI pin input 6 TMIFEG 0 R/W TMIF Edge Select 0: Detects a falling edge of the TMIF pin input 1: Detects a rising edge of the TMIF pin input 5 ADTRGNEG 0 R/W ADTRG Edge Select 0: Detects a falling edge of the ADTRG pin input 1: Detects a rising edge of the ADTRG pin input 4 IEG4 0 R/W IRQ4 Edge Select 0: Detects a falling edge of the IRQ4 pin input 1: Detects a rising edge of the IRQ4 pin input 3 IEG3 0 R/W IRQ3 Edge Select 0: Detects a falling edge of the IRQ3 pin input 1: Detects a rising edge of the IRQ3 pin input 2 1 IEG1 1 0 R/W Reserved This bit is always read as 1 and cannot be modified. IRQ1 Edge Select 0: Detects a falling edge of the IRQ1 pin input 1: Detects a rising edge of the IRQ1 pin input 0 IEG0 0 R/W IRQ0 Edge Select 0: Detects a falling edge of the IRQ0 pin input 1: Detects a rising edge of the IRQ0 pin input
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Section 4 Interrupt Controller
4.3.2
Wakeup Edge Select Register (WEGR)
WEGR selects the sense of an edge that generates interrupt requests of the WKP7 to WKP0 pins.
Bit 7 Bit Name WKEGS7 Initial Value 0 R/W R/W Description WKP7 Edge Select 0: Detects a falling edge of the WKP7 pin input 1: Detects a rising edge of the WKP7 pin input 6 WKEGS6 0 R/W WKP6 Edge Select 0: Detects a falling edge of the WKP6 pin input 1: Detects a rising edge of the WKP6 pin input 5 WKEGS5 0 R/W WKP5 Edge Select 0: Detects a falling edge of the WKP5 pin input 1: Detects a rising edge of the WKP5 pin input 4 WKEGS4 0 R/W WKP4 Edge Select 0: Detects a falling edge of the WKP4 pin input 1: Detects a rising edge of the WKP4 pin input 3 WKEGS3 0 R/W WKP3 Edge Select 0: Detects a falling edge of the WKP3 pin input 1: Detects a rising edge of the WKP3 pin input 2 WKEGS2 0 R/W WKP2 Edge Select 0: Detects a falling edge of the WKP2 pin input 1: Detects a rising edge of the WKP2 pin input 1 WKEGS1 0 R/W WKP1 Edge Select 0: Detects a falling edge of the WKP1 pin input 1: Detects a rising edge of the WKP1 pin input 0 WKEGS0 0 R/W WKP0 Edge Select 0: Detects a falling edge of the WKP0 pin input 1: Detects a rising edge of the WKP0 pin input
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Section 4 Interrupt Controller
4.3.3
Interrupt Enable Register 1 (IENR1)
IENR1 enables the RTC, WKP7 to WKP0, IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC interrupts.
Bit 7 Bit Name IENRTC Initial Value 0 R/W R/W Description RTC Interrupt Request Enable The RTC interrupt request is enabled when this bit is set to 1. 6 5 IENWP 1 0 R/W Reserved This bit is always read as 1 and cannot be modified. Wakeup Interrupt Request Enable The WKP7 to WKP0 interrupt requests are enabled when this bit is set to 1. 4 IEN4 0 R/W IRQ4 Interrupt Request Enable The IRQ4 interrupt request is enabled when this bit is set to 1. 3 IEN3 0 R/W IRQ3 Interrupt Request Enable The IRQ3 interrupt request is enabled when this bit is set to 1. 2 IENEC2 0 R/W IRQAEC Interrupt Request Enable The IRQAEC interrupt request is enabled when this bit is set to 1. 1 IEN1 0 R/W IRQ1 Interrupt Request Enable The IRQ1 interrupt request is enabled when this bit is set to 1. 0 IEN0 0 R/W IRQ0 Interrupt Request Enable The IRQ0 interrupt request is enabled when this bit is set to 1.
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Section 4 Interrupt Controller
4.3.4
Interrupt Enable Register 2 (IENR2)
IENR2 enables the direct transition, A/D converter, timer G, timer F, timer C, and asynchronous event counter interrupts.
Bit 7 Bit Name IENDT Initial Value 0 R/W R/W Description Direct Transition Interrupt Request Enable The direct transition interrupt request is enabled when this bit is set to 1. 6 IENAD 0 R/W A/D Converter Interrupt Request Enable The A/D converter interrupt request is enabled when this bit is set to 1. 5 4 -- IENTG 0 0 R/W R/W Reserved This bit can be read from or written to. Timer G Interrupt Request Enable The timer G interrupt request is enabled when this bit is set to 1. 3 IENTFH 0 R/W Timer FH Interrupt Request Enable The timer FH interrupt request is enabled when this bit is set to 1. 2 IENTFL 0 R/W Timer FL Interrupt Request Enable The timer FL interrupt request is enabled when this bit is set to 1. 1 IENTC 0 R/W Timer C Interrupt Request Enable The timer C interrupt request is enabled when this bit is set to 1. 0 IENEC 0 R/W Asynchronous Event Counter Interrupt Request Enable The asynchronous event counter interrupt request is enabled when this bit is set to 1.
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Section 4 Interrupt Controller
4.3.5
Interrupt Request Register 1 (IRR1)
IRR1 indicates the IRQ0, IRQ1, IRQ3, IRQ4, and IRQAEC interrupt request status.
Bit 7 to 5 Initial Bit Name Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 IRRI4 0 R/W IRQ4 Interrupt Request Flag [Setting condition] The IRQ4 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] The IRQ3 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 2 IRREC2 0 R/W IRQAEC Interrupt Request Flag [Setting condition] The IRQAEC pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 1 IRRI1 0 R/W IRQ1 Interrupt Request Flag [Setting condition] The IRQ1 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit
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Section 4 Interrupt Controller
Bit 0
Initial Bit Name Value IRRI0 0
R/W R/W
Description IRQ0 Interrupt Request Flag [Setting condition] The IRQ0 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit
4.3.6
Interrupt Request Register 2 (IRR2)
IRR2 indicates the state of the direct transition, A/D converter, timer G, timer F, timer C, and asynchronous event counter interrupt requests.
Bit 7 Bit Name IRRDT Initial Value 0 R/W R/W Description Direct Transition Interrupt Request Flag [Setting condition] Execution of a SLEEP instruction while the DTON bit in SYSCR2 is set to 1, so that a direct transition is made to sleep mode [Clearing condition] Writing of 0 to this bit 6 IRRAD 0 R/W A/D Converter Interrupt Request Flag [Setting condition] When A/D conversion ends [Clearing condition] Writing of 0 to this bit 5 4 -- IRRTG 0 0 -- R/W Reserved This bit is always read as 0 and cannot be modified. Timer G Interrupt Request Flag [Setting condition] The timer G input capture or overflow occurs. [Clearing condition] Writing of 0 to this bit
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Section 4 Interrupt Controller
Bit 3
Bit Name IRRTFH
Initial Value 0
R/W R/W
Description Timer FH Interrupt Request Flag [Setting condition] The timer FH compare match or overflow occurs [Clearing condition] Writing of 0 to this bit
2
IRRTFL
0
R/W
Timer FL Interrupt Request Flag [Setting condition] The timer FL compare match or overflow occurs [Clearing condition] Writing of 0 to this bit
1
IRRTC
0
R/W
Timer C Interrupt Request Flag [Setting condition] The timer C overflow or underflow occurs. [Clearing condition] Writing of 0 to this bit
0
IRREC
0
R/W
Asynchronous Event Counter Interrupt Request Flag [Setting condition] The asynchronous event counter overflows [Clearing condition] Writing of 0 to this bit
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Section 4 Interrupt Controller
4.3.7
Wakeup Interrupt Request Register (IWPR)
IWPR has the WKP7 to WKP0 interrupt request status flags.
Bit 7 Bit Name IWPF7 Initial Value 0 R/W R/W Description WKP7 Interrupt Request Flag [Setting condition] The WKP7 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 6 IWPF6 0 R/W WKP6 Interrupt Request Flag [Setting condition] The WKP6 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 5 IWPF5 0 R/W WKP5 Interrupt Request Flag [Setting condition] The WKP5 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 4 IWPF4 0 R/W WKP4 Interrupt Request Flag [Setting condition] The WKP4 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] The WKP3 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit
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Section 4 Interrupt Controller
Bit 2
Bit Name IWPF2
Initial Value 0
R/W R/W
Description WKP2 Interrupt Request Flag [Setting condition] The WKP2 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit
1
IWPF1
0
R/W
WKP1 Interrupt Request Flag [Setting condition] The WKP1 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit
0
IWPF0
0
R/W
WKP0 Interrupt Request Flag [Setting condition] The WKP0 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] Writing of 0 to this bit
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Section 4 Interrupt Controller
4.3.8
Interrupt Priority Registers A to F (IPRA to IPRF)
IPR sets mask levels (levels 2 to 0) for interrupts other than the NMI and address break. The correspondence between interrupt sources and IPR settings is shown in table 4.2. Setting a value in the range from H'0 to H'3 in the 2-bit groups of bits 7 and 6, 5 and 4, 3 and 2, and 1 and 0 sets the mask level of the corresponding interrupt. Bits 3 to 0 in IPRE and bits 1 and 0 in IPRF are reserved.
Bit 7 6 Initial Bit Name Value IPRn7 IPRn6 0 0 R/W R/W R/W Description Set the mask level of the corresponding interrupt source. 00: Mask level 0 (Lowest) 01: Mask level 1 1x: Mask level 2 (Highest) 5 4 IPRn5 IPRn4 0 0 R/W R/W Set the mask level of the corresponding interrupt source. 00: Mask level 0 (Lowest) 01: Mask level 1 1x: Mask level 2 (Highest) 3 2 IPRn3 IPRn2 0 0 R/W R/W Set the mask level of the corresponding interrupt source. 00: Mask level 0 (Lowest) 01: Mask level 1 1x: Mask level 2 (Highest) 1 0 IPRn1 IPRn0 0 0 R/W R/W Set the mask level of the corresponding interrupt source. 00: Mask level 0 (Lowest) 01: Mask level 1 1x: Mask level 2 (Highest) [Legend] x: Don't care n = A to F
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Section 4 Interrupt Controller
4.3.9
Interrupt Mask Register (INTM)
INTM is an 8-bit readable/writable register that controls 3-level interrupt masking depending on the combination of the INTM0 and INTM1 bits.
Bit 7 to 2 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 1 0 INTM1 INTM0 0 0 R/W R/W Set the interrupt mask level. 1x: Mask an interrupt with mask level 1 or less 01: Mask an interrupt with mask level 0 00: Accept all interrupts [Legend] x: Don't care
4.4
4.4.1
Interrupt Sources
External Interrupts
There are 14 external interrupts: NMI, WKP7 to WKP0, IRQ4, IRQ3, IRQAEC, IRQ1, and IRQ0. (1) NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the state of the I bit in CCR. The NMIEG bit in IEGR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. (2) WKP7 to WKP0 Interrupts
WKP7 to WKP0 interrupts are requested by the rising or falling edge input signals at the WKP7 to WKP0 pins. When the rising or falling edge is input while the WKP7 to WKP0 pin functions are selected by PMR5, the corresponding bit in IWPR is set to 1 and an interrupt request is generated. Clearing the IENWP bit in IENR1 to 0 disables the wakeup interrupt request to be accepted. Setting the I bit in CCR to 1 masks all interrupts.
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Section 4 Interrupt Controller
When exception handling for the WKP7 to WKP0 interrupts is accepted, the I bit in CCR is set to 1. The interrupt mask level can be set by IPR. (3) IRQ4, IRQ3, IRQ1, and IRQ0 Interrupts
IRQ4, IRQ3, IRQ1, and IRQ0 interrupts are requested by input signals at IRQ4, IRQ3, IRQ1, and IRQ0 pins. Using the IEG4, IEG3, IEG1, and IEG0 bits in IEGR, it is possible to select whether an interrupt is generated by a rising or falling edge at IRQ4, IRQ3, IRQ1, and IRQ0 pins. When the specified edge is input while the IRQ4, IRQ3, IRQ1, and IRQ0 pin functions are selected by PFCR, PMRF, PMRE, PMRB, and PMR9, the corresponding bit in IRR1 is set to 1 and an interrupt request is generated. Clearing the IEN4, IEN3, IEN1, and IEN0 bits in IENR1 to 0 disables the interrupt request to be accepted. Setting the I bit in CCR to 1 masks all interrupts. The interrupt mask level can be set by IPR. (4) IRQAEC Interrupts
An IRQAEC interrupt is requested by an input signal at the IRQAEC pin or IECPWM (PWM output for the AEC). When the IRQAEC pin is used as an external interrupt pin, clear the ECPWME bit in AEGSR to 0. Using the AIEGS1 and AIEGS0 bits in AEGSR, it is possible to select whether an interrupt is generated by a rising edge, falling edge, or both edges. When the IENEC2 bit in IENR1 is set to 1 and the specified edge is input, the corresponding bit in IRR1 is set to 1 and an interrupt request is generated. When exception handling for the IRQAEC interrupt is accepted, the I bit in CCR is set to 1. The interrupt mask level can be set by IPR.
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Section 4 Interrupt Controller
4.4.2
Internal Interrupts
Internal interrupts generated from the on-chip peripheral modules have the following features: * For each on-chip peripheral module, there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. Internal interrupts can be controlled independently. If an enable bit is set to 1, an interrupt request is sent to the interrupt controller. * The interrupt mask level can be set by IPR.
4.5
Interrupt Exception Handling Vector Table
Table 4.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For priorities, the lower the vector number, the higher the mask level. Priorities within a module are fixed. Interrupt mask levels other than NMI and address break can be modified by IPR.
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Section 4 Interrupt Controller
Table 4.2
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Name Reset NMI Break conditions satisfied IRQ0 IRQ1 IRQAEC IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Vector Number 0 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Vector Address H'000000 H'00000C H'000014 H'000018 H'00001C H'000020 H'000024 H'000028 H'00002C H'000030 H'000034 H'000038 H'00003C H'000040 H'000044 H'000048 H'00004C H'000050 H'000054 H'000058 H'00005C H'000060 H'000064 H'000068 Low IPRB5, IPRB4 IPRB7, IPRB6 IPRA7, IPRA6 IPRA5, IPRA4 IPRA3, IPRA2 IPRA1, IPRA0 IPR Mask Level High
Origin of Interrupt Source RES, WDT NMI Address break External pins
RTC
0.25-second overflow 0.5-second overflow Second periodic overflow Minute periodic overflow Hour periodic overflow Day periodic overflow Week periodic overflow Free-running overflow
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Section 4 Interrupt Controller Origin of Interrupt Source WDT AEC TPU_1 Vector Number 27 28 29 30 31 32 33 34 35 36 Mask Level High
Name WDT overflow (interval timer) AEC overflow TG1A (TG1A input capture/compare match) TG1B (TG1B input capture/compare match) TCI1V (overflow 1)
Vector Address H'00006C H'000070 H'000074 H'000078 H'00007C H'000080 H'000084 H'000088 H'00008C H'000090 H'000094
IPR IPRB3, IPRB2 IPRB1, IPRB0 IPRC7, IPRC6
TPU_2
TG2A (TG2A input capture/compare match) TG2B (TG2B input capture/compare match) TCI2V (overflow 2)
IPRC5, IPRC4
Timer F
Timer FL compare match Timer FL overflow Timer FH compare match Timer FH overflow
IPRC3, IPRC2
SCI4*
Receive data full/transmit 37 data empty Transmit end/receive error Transmit completion/transmit data empty Receive data full/overrun error Framing error/parity error Transmit completion/transmit data empty Receive data full/overrun error Framing error/parity error Transmit data empty/transmit end Receive data full/stop condition detection NACK detection Arbitration/overrun error A/D conversion end 38
IPRC1, IPRC0
SCI3_1
H'000098
IPRD7, IPRD6
SCI3_2
39
H'00009C
IPRD5, IPRD4
IIC2
40
H'0000A0
IPRD3, IPRD2
10-bit A/D
42 43
H'0000A8 H'0000AC
IPRE7, IPRE6 IPRE5, IPRE4 Low
(SLEEP instruction Direct transition execution)
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Section 4 Interrupt Controller Origin of Interrupt Source Timer C Timer G SCI3_3 Vector Number 53 54 55 Mask Level High
Name Timer C overflow/underflow Timer G input capture Timer G overflow Transmit completion/transmit data empty Receive data full/overrun error Framing error/parity error
Vector Address H'0000D4 H'0000D8 H'0000DC
IPR IPRF7, IPRF6 IPRF5, IPRF4 IPRF3, IPRF2
Low
Note:
*
Supported only by the flash version.
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Section 4 Interrupt Controller
4.6
Operation
NMI and address break interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts, WKP interrupts, and on-chip peripheral module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 4.3 shows the interrupt control states. Figure 4.2 shows a flowchart of the interrupt acceptance operation. Four-level interrupt masking is controlled according to the combination of the I bit in CCR and the INTM1 and INTM0 bits in INTM. Table 4.3
CCR I 1 0 INTM1 x 1 0 0 [Legend] x: Don't care
Interrupt Control States
INTM INTM0 x x 1 0 States All interrupts other than NMI and address break are masked. Interrupts with mask level 1 or less are masked. Interrupts with mask level 0 are masked. All interrupts are accepted.
1. If an interrupt source whose enable bit is set to 1 occurs, an interrupt request is sent to the interrupt controller. 2. With referring to the INTM1 and INTM0 bits in INTM and the I bit in CCR, control the following. The interrupt request is held pending when the I bit is set to 1. When the I bit is cleared to 0 and INTM1 bit is set to 1, interrupts with mask level 1 or less are held pending. When the I bit is cleared to 0, INTM1 bit is cleared to 0, and INTM0 bit is set to 1, interrupt requests with mask level 0 are held pending. When the I bit, INTM1 bit, and INTM0 bit are all cleared to 0, all interrupt requests are accepted.
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Section 4 Interrupt Controller
3. If a conflict occurs between interrupt requests that are not held pending due to the settings of the IMTM1, IMTN0 bits in INTM or the I bit in CCR, the interrupt request with the highest mask level according to table 4.2 is selected regardless of the IPR setting. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. PC and CCR are saved to the stack area by interrupt exception handling. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI and address break. 7. The CPU generates a vector address for the accepted interrupt and starts interrupt handling by reading the interrupt routine start address in the vector table.
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Section 4 Interrupt Controller
Program execution state
Interrupt generated? Yes NMI or address break? Yes
No
No
INTM1 = 0? INTM0 = 0? Yes
No
INTM1 = 0? INTM0 = 1? No Yes Mask level 1 or 2 interrupt? Yes
No
I = 0? Yes
No
Mask level 2 interrupt? Yes
No
No No I = 0? Yes
I = 0? Yes
Save PC and CCR I1
Held pending
Set vector address Branch to interrupt handling routine
Figure 4.2 Flowchart of Procedure Up to Interrupt Acceptance 4.6.1 Interrupt Exception Handling Sequence
Figure 4.3 shows the interrupt exception handling sequence.
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Interrupt accepted
Instruction prefetch Stack
REJ09B0309-0200
Internal processing Vector fetch Internal processing Instruction prefetch of interrupt handling routine (1) (3) (5) (7) (9) (11) (13) High (2) (4) (6) (8) (10) (12) (14) (9)(11): Vector address (10)(12): Interrupt handling routine start address (Vector address contents) (13): (14): Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine
Interrupt level determination Wait for end of instruction
Section 4 Interrupt Controller
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Interrupt request signal
Internal address bus
Internal read signal
Internal write signal
Internal data bus
(1):
Instruction prefetch address (Not executed. This is the contents of the saved PC and the return address.)
(2)(4): Instruction code (Not executed.)
Figure 4.3 Interrupt Exception Handling Sequence
(3):
Instruction prefetch address (Not executed.)
(5):
SP-2
(7):
SP-4
(6)(8): Saved PC and saved CCR
Section 4 Interrupt Controller
4.6.2
Interrupt Response Times
Table 4.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 4.4
No. 1 2 3 4 5 6
Interrupt Response Times (States)
Number of States 1 or 2* 1 to 23 4 4
2 3 1
Execution Status Interrupt mask level determination Maximum number of wait states until executing instruction ends PC, CCR stack Vector fetch Instruction fetch*
4 4 18 to 41
Internal processing* Total
Notes: 1. One state in case of an internal interrupt (2 states in case of an external interrupt). 2. Prefetch after interrupt acceptance and interrupt handling routine prefetch. 3. Internal processing after interrupt acceptance and internal processing after vector fetch.
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Section 4 Interrupt Controller
4.7
4.7.1
Usage Notes
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with a higher mask level than that interrupt, interrupt exception handling will be executed for the interrupt with a higher mask level, and the interrupt with a lower mask level will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 4.4 shows an example in which the TGIEA bit in TIER of the 16-bit timer pulse unit (TPU) is cleared to 0.
TIER write cycle by CPU TGIA exception handling
Internal address bus Internal write signal
TIER address
TGIEA
TGIA
TGIA interrupt signal
Figure 4.4 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
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Section 4 Interrupt Controller
4.7.2
Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. When an interrupt request is generated, an interrupt is requested to the CPU after the interrupt controller has determined the mask level. At that time, if the CPU is executing an instruction that disables interrupts, the CPU always executes the next instruction after the instruction execution is completed. 4.7.3 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, even if an interrupt request other than the NMI is issued during transfer, the interrupt is not accepted until the transfer is completed. If the NMI interrupt request is issued, NMI exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an NMI interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
4.7.4
IENR Clearing
When an interrupt request is disabled by clearing the interrupt enable register or when the interrupt request register is cleared, the interrupt request should be masked (I bit = 1). If the above operation is executed while the I bit is 0 and contention between the instruction execution and the interrupt request generation occurs, exception handling, which corresponds to the interrupt request generated after instruction execution of the above operation is completed, is executed.
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Section 4 Interrupt Controller
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Section 5 Clock Pulse Generator
Section 5 Clock Pulse Generator
The clock pulse generator incorporated into this LSI consists of a system clock pulse generator circuit that consists of a system clock oscillator, system clock divider, and an on-chip oscillator for the system clock, and a subclock pulse generator circuit that consists of a subclock oscillator and subclock divider. Figure 5.1 is a block diagram of the clock pulse generator.
IRQAEC On-chip oscillator for system clock
*
ROSC OSC1 OSC2 System clock oscillator OSC (fOSC) OSC (fOSC) System clock divider
OSC OSC/8 OSC/16 OSC/32 OSC/64
Prescaler S (17 bits) W /2 to /131072
System clock pulse generator circuit W/2 X1 X2 Subclock oscillator W (fW) Subclock divider W/4 W/8
W/4 SUB Prescaler W (8 bits) W/8 to W/1024
Subclock pulse generator circuit W/2
Note: * The system clock can be output from the on-chip oscillator for the system clock or system clock oscillator by the input level of the IRQAEC pin during an internal reset except for the one by the watchdog timer.
Figure 5.1 Block Diagram of Clock Pulse Generator The basic clock signals that drive the CPU and on-chip peripheral modules are the system clock () and subclock (SUB). Prescaler S frequency-divides the clock signal S to produce clock signals at rates from /131072 to /2, and prescaler W frequency-divides the watch clock w/4, which is the watch clock frequency-divided by four, to produce clock signals from at rates from w/1024 to w/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules. Since the on-chip oscillator for the system clock is available, the system clock can be selected to be output from the on-chip oscillator for the system clock or system clock oscillator by the input level of the IRQAEC pin.
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Section 5 Clock Pulse Generator
5.1
Register Description
* SUB32k control register (SUB32CR) * Oscillator Control Register (OSCCR) 5.1.1 SUB32k Control Register (SUB32CR)
SUB32CR controls whether the subclock oscillator is operating or stopped.
Bit 7 Bit Name 32KSTOP Initial Value 0 R/W R/W Description Subclock Oscillator Operation Control Controls whether the subclock oscillator is operating or stopped. When the subclock oscillator is not used, set this bit to 1. 0: Subclock oscillator operates 1: Subclock oscillator stops 6 5 to 0 0 All 0 R/W Reserved This bit can be read from or written to. Reserved These bits are always read as 0 and cannot be modified.
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Section 5 Clock Pulse Generator
5.1.2
Oscillator Control Register (OSCCR)
OSCCR is used to control the built-in feedback resistor and includes the IRQAEC and OSC flags.
Bit 7 6 Bit Name -- RFCUT Initial Value 0 0 R/W R/W R/W Description Reserved This bit can be read from or written to. Built-In Feedback Resistor Control Selects whether to use the built-in feedback resistor of the system clock oscillator when the external clock is being input or the on-chip oscillator for the system clock is selected. When the external clock is being input or the on-chip oscillator for the system clock is in use, set this bit and then temporarily enter standby mode, watch mode, or subactive mode. After any of these modes is entered, the built-in feedback oscillator is used or not used according to this specification. 0: Built-in feedback resistor is used with the system clock oscillator 1: Built-in feedback resistor is not used with the system clock oscillator 5 4 3 2 -- -- -- IRQAECF 0 0 0 --* R/W R/W R/W R Reserved The write value should always be 0. Reserved This bit can be read from or written to. Reserved The write value should always be 0. IRQAEC Flag This bit indicates the level at which the IRQAEC pin is to be set during resets. 0: IRQAEC pin set to GND during resets 1: IRQAEC pin set to Vcc during resets
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Section 5 Clock Pulse Generator
Bit 1
Bit Name OSCF
Initial Value --*
R/W R
Description OSC Flag This bit indicates which oscillator is acting as the system clock pulse generator. 0: The system clock oscillator is the generator (operation of the on-chip oscillator for system clock stopped) 1: The on-chip oscillator for the system clock is the generator (system clock oscillator stopped)
0 Note: *
--
0
R/W
Reserved The write value should always be 0.
The initial value depends on the IRQAEC pin state. For details, see table 5.1.
5.2
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing an external clock input. The system clock oscillator or the on-chip oscillator for the system clock is selectable, as shown in figure 5.1. For details on how to select the oscillator, see section 5.2.4, Selecting On-Chip Oscillator for System Clock. 5.2.1 Connecting Crystal Resonator
Figure 5.2 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. For precautionary notes on connection of the crystal resonator, see section 5.5.2, Notes on Board Design.
C1 OSC1 C2 C1, C2 Product Type Recommended Value NR-18 12 pF 20%
OSC2
Frequency 4.19 MHz
Manufacturer NIHON DEMPA KOGYO.,LTD.
Figure 5.2 Typical Connection to Crystal Resonator
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Section 5 Clock Pulse Generator
5.2.2
Connecting Ceramic Resonator
Figure 5.3 shows a typical method of connecting a ceramic resonator.
C1 OSC1 C2 OSC2
Frequency Manufacturer Product Type C 1 , C2 Recommended Value
4.194 MHz Murata Manufacturing CSTLS4M19G53-B0 15 pF (on-chip) CSTLS4M19G56-B0 47 pF (on-chip) Co., Ltd.
Figure 5.3 Typical Connection to Ceramic Resonator 5.2.3 External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.4 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
External clock input
OSC2
Open
Figure 5.4 Example of External Clock Input
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Section 5 Clock Pulse Generator
5.2.4
Selecting On-Chip Oscillator for System Clock
The on-chip oscillator is selected by the input level on the IRQAEC pin during a reset*. The selection of the system clock oscillator or on-chip oscillator for the system clock is as listed in table 5.1. The level being input on the IRQAEC pin during a reset should be fixed to either Vcc or GND, depending on the oscillator type to be selected. The level will be determined upon reset cancellation When the on-chip oscillator for the system clock is selected, connection of a resonator to OSC1 or OSC2 is not necessary. In this case, the OSC1 pin should be fixed to Vcc or GND. The OSC2 pin should be left open. Notes: When programming or erasing the flash memory, e.g. by on-board programming, the system clock oscillator should always be selected. Use of the on-chip emulator requires either a connected resonator or the supply of an external clock signal, even if the on-chip oscillator for the system clock is selected. * This reset represents an external reset or power-on reset, but not a reset by the watchdog timer. Table 5.1 Selection of the System Clock Oscillator or On-Chip Oscillator for the System Clock
Oscillator of System Clock Pulse Generator Circuit OSCF System clock oscillator 0 IRQAECF 0 1
IRQAEC Input Level (During a Reset) Low High
On-chip oscillator for system clock 1
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Section 5 Clock Pulse Generator
5.3
Subclock Generator
Subclocks can be supplied either by connecting a crystal resonator, or by providing external clock input. 5.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator
Figure 5.5 shows an example of connection to a 32.768-kHz or 38.4-kHz crystal resonator. Notes in section 5.5.2, Notes on Board Design, also apply to this connection.
C1 X1
X2 C2 Frequency 38.4 kHz 32.768 kHz
Note: Consult with the crystal resonator manufacturer to determine the circuit constants. Manufacturer Epson Toyocom Epson Toyocom Product Name C-4-TYPE C-001R Equivalent Series Resistance 30 k (max.) 35 k (max.)
C1 = C2 = 7 pF (typ.)
Figure 5.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator 1. When using a resonator other than the above, ensure optimal conditions by conducting sufficient evaluation of consistency in cooperation with the manufacturer of the resonator. Even if the above resonators or products equivalent to them are implemented, their oscillation characteristics are affected by the board design. Be sure to use the actual board to evaluate consistency as a system. 2. The consistency as a system has to be verified not only in a reset state (i.e., the RES pin is driven low) but also in a state where a reset state has been exited (i.e., the low-level RES signal has been driven high).
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Section 5 Clock Pulse Generator
Figure 5.6 shows the equivalent circuit of the crystal resonator.
CS LS X1 RS X2
CO
C O = 0.9 pF (typ.) R S = 50 k (typ.) W = 32.768 kHz/38.4kHz
Figure 5.6 Equivalent Circuit of 32.768-kHz Crystal Resonator 5.3.2 Pin Connection when not Using Subclock
When the subclock is not used, connect the X1 pin to GND and leave the X2 pin open, as shown in figure 5.7.
X1 GND X2 Open
Figure 5.7 Pin Connection when not Using Subclock
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Section 5 Clock Pulse Generator
5.3.3
How to Input the External Clock
Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 5.8.
X1
External clock input
X2
Open
Figure 5.8 Pin Connection when Inputting External Clock
Frequency Duty Subclock (w) 45% to 55%
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Section 5 Clock Pulse Generator
5.4
Prescalers
This LSI has two prescalers (prescaler S and prescaler W), and each has its own input clock signal. Prescaler S is a 17-bit counter that has the system clock () as its input clock. Its prescaled outputs provide the internal clock signals that drive the on-chip peripheral modules. Prescaler W is an 8-bit counter that has a frequency-divided signal (W/4) derived from the watch clock (W) as its input clock. Its prescaled outputs provide the internal clock signals that drive the on-chip peripheral modules. 5.4.1 Prescaler S
Prescaler S is a 17-bit counter using the system clock () as its input clock. A divided output is used as an internal clock of an on-chip peripheral module. Prescaler S is initialized to H'00000 at a reset, and starts counting up on exit from the reset state. Prescaler S stops and is initialized to H'00000 in standby mode, watch mode, subactive mode, and subsleep mode. The CPU cannot read from or write to prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. In active (mediumspeed) mode and sleep mode (medium-speed), the clock input to prescaler S is determined by the division ratio designated by the MA1 and MA0 bits in SYSCR2. 5.4.2 Prescaler W
Prescaler W is an 8-bit counter that has a frequency-divided signal (W/4) derived from the watch clock (W) as its input clock. This signal is further divided to produce internal clock signals for the on-chip peripheral modules. Prescaler W is initialized to H'00 by a reset, and starts counting up on exit from the reset state. Prescaler W stops in standby mode, but continues to operate in watch mode, subactive mode, and subsleep mode.
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Section 5 Clock Pulse Generator
5.5
5.5.1
Usage Notes
Note on Resonators and Resonator Circuits
Resonator characteristics are closely related to board design. Therefore, resonators should be assigned after being carefully evaluated by the user in the masked ROM version and flash memory version, with referring to the examples shown in this section. Resonator circuit constants will differ depending on a resonator, stray capacitance in its mounting circuit, and other factors. Suitable constants should be determined in consultation with the resonator manufacturer. Design the circuit so that the oscillator pin is never applied voltages exceeding its maximum rating. Figure 5.9 shows an example of crystal and ceramic resonator arrangement.
Vcc OSC2 Vss OSC1 RES X2 X1 NMI
(Vss)
Figure 5.9 Example of Crystal and Ceramic Resonator Arrangement
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Section 5 Clock Pulse Generator
Figure 5.10 (1) shows an example measuring circuit with the negative resistance recommended by the resonator manufacturer. Note that if the negative resistance of the circuit is less than that recommended by the resonator manufacturer, it may be difficult to start the main oscillator. If it is determined that oscillation does not occur because the negative resistance is lower than the level recommended by the resonator manufacturer, the circuit must be modified as shown in figure 5.10 (2) through (4). Which of the modification suggestions to use and the capacitor capacitance should be decided based upon evaluation results such as the negative resistance and the frequency deviation.
Modification point OSC1 C1 C1 OSC1
OSC2 C2 Negative resistance, addition of -R (1) Negative Resistance Measuring Circuit C2
OSC2
(2) Oscillator Circuit Modification Suggestion 1
Modification point
Modification point OSC1 C1 C1
C3 OSC1
C2
OSC2 C2
OSC2
(3) Oscillator Circuit Modification Suggestion 2
(4) Oscillator Circuit Modification Suggestion 3
Figure 5.10 Negative Resistance Measurement and Circuit Modification Suggestions
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Section 5 Clock Pulse Generator
5.5.2
Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.11).
Avoid Signal A Signal B
C1 OSC1 C2 OSC2
Figure 5.11 Example of Incorrect Board Design Note: When a crystal resonator or ceramic resonator is connected, consult with the crystal resonator and ceramic resonator manufacturers to determine the circuit constants because the constants differ according to the resonator, stray capacitance of the mounting circuit, and so on. 5.5.3 Definition of Oscillation Stabilization Wait Time
Figure 5.12 shows the oscillation waveform (OSC2), system clock (), and microcontroller operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with a resonator connected to the system clock oscillator. As shown in figure 5.12, when a transition is made to active (high-speed/medium-speed) mode, from standby mode, watch mode, or subactive mode, in which the system clock oscillator is halted, the sum of the following two times (oscillation start time and wait time) is required. (1) Oscillation Stabilization Time
The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the system clock starts to be generated.
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Section 5 Clock Pulse Generator
(2)
Wait Time
After the system clock is generated, the time required for the amplitude of the oscillation waveform to increase, the oscillation frequency to stabilize, and the CPU and peripheral functions to begin operating.
Oscillation waveform (OSC2)
System clock () Oscillation start time
Wait time
Operating mode
Standby mode, watch mode, or subactive mode
Oscillation stabilization wait time
Active (high-speed) mode or active (medium-speed) mode
Interrupt accepted
Figure 5.12 Oscillation Stabilization Wait Time As the oscillation stabilization wait time required is the same as the oscillation stabilization time (trc) at power-on, specified in the AC characteristics, set the STS2 to STS0 bits in SYSCR1 to specify the time longer than the oscillation stabilization time (trc). Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an resonator connected to the system clock oscillator, careful evaluation must be carried out on the mounting circuit before deciding the oscillation stabilization wait time. For the wait time, secure the time required for the amplitude of the oscillation waveform to increase and the oscillation frequency to stabilize. In addition, since the oscillation start time differs according to mounting circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the resonator manufacturer. 5.5.4 Note on Subclock Stop State
To stop the subclock, a state transition should not be made except to mode in which the system clock operates. If the state transition is made to other mode, it may result in incorrect operation.
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Section 5 Clock Pulse Generator
5.5.5
Note on the Oscillation Stabilization of Resonators
When a microcontroller operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. Depending on the individual resonator characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an unstable system clock and incorrect operation of the microcontroller. If incorrect operation occurs, change the setting of the standby timer select bits 3 to 0 (STS3 to STS0) (bit 0 in the system control register 3 (SYSCR3) and bits 6 to 4 in the system control register 1 (SYSCR1)) to give a longer wait time. For example, if incorrect operation occurs with a wait time setting of 1,024 states, check the operation with a wait time setting of 2,048 states or more. If the same kind of incorrect operation occurs after a reset as after a state transition, hold the RES pin low for a longer period. 5.5.6 Note on Using On-Chip Power-On Reset
The power-on reset circuit in this LSI adjusts the reset clear time by the capacitor capacitance, which is externally connected to the RES pin. The external capacitor capacitance should be adjusted to secure the oscillation stabilization time before reset clearing. For details, refer to section 23, Power-On Reset Circuit. 5.5.7 Note on Using the On-Chip Emulator
When using the on-chip emulator, programming and erasure of the flash memory require an accurate system clock signal. The frequency of the on-chip oscillator for the system clock varies according to voltage and temperature conditions. Thus, when the on-chip emulator is in use, a resonator must be connected between the OSC1 and OSC2 pins or an external clock signal must be supplied. In this case, the on-chip emulator is driven by the on-chip oscillator for the system clock in the execution of user programs, and by the system clock oscillator in the programming and erasure of the flash memory. This selection is achieved by fixing the level of the IRQAEC pin to the low level during the reset period of the on-chip emulator.
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Section 5 Clock Pulse Generator
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Section 6 Power-Down Modes
Section 6 Power-Down Modes
This LSI has eight modes of operation after a reset. These include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by selectively halting on-chip module functions. * Active (medium-speed) mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from OSC/8, OSC/16, OSC/32, and OSC/64. * Subactive mode The CPU and all on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from W/2, W/4, and W/8. * Sleep (high-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Sleep (medium-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from OSC/8, OSC/16, OSC/32, and OSC/64. * Subsleep mode The CPU halts. The on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from W/2, W/4, and W/8. * Watch mode The CPU halts. The on-chip peripheral modules are operable on the subclock. * Standby mode The CPU and all on-chip peripheral modules halt. * Module standby function Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. Note: In this manual, active (high-speed) mode and active (medium-speed) mode are collectively called active mode, and sleep (high-speed) mode and sleep (medium-speed) mode are collectively called sleep mode.
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Section 6 Power-Down Modes
6.1
Register Descriptions
The registers related to power-down modes are as follows. * System control register 1 (SYSCR1) * System control register 2 (SYSCR2) * System control register 3 (SYSCR3) * Clock halt registers 1 to 3 (CKSTPR1 to CKSTPR3) 6.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes with SYSCR2 and SYSCR3.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Selects the mode to transit after the execution of the SLEEP instruction. 0: A transition is made to sleep mode or subsleep mode. 1: A transition is made to standby mode or watch mode. For details, see table 6.2. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 Specify the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or watch mode to active mode or sleep mode. These bits should be specified together with the STS3 bit in SYSCR3 according to the operating frequency so that the wait time is at least equal to the oscillation stabilization time. The relationship between the specified value and the number of wait states is shown in table 6.1. When an external clock is to be used, the minimum value (STS3 = 0, STS2 = 1, STS1 = 0, STS0 = 1) is recommended. When the on-chip oscillator for the system clock is to be used, four states (STS3 = 1, STS2 = 1, STS1 = 0, STS0 = 1) are recommended. If a setting other than the recommended value is made, operation may start before the end of the wait time.
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Section 6 Power-Down Modes
Bit 3
Bit Name LSON
Initial Value 0
R/W R/W
Description Selects the system clock () or subclock (SUB) as the CPU operating clock when watch mode is cleared. 0: The CPU operates on the system clock () 1: The CPU operates on the subclock (SUB)
2
TMA3
0
R/W
Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY and LSON in SYSCR1 and bits DTON and MSON in SYSCR2. For details, see table 6.2. Active Mode Clock Select 1 and 0 Select the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. The MA1 and MA0 bits should be written to in active (high-speed) mode or subactive mode. 00: OSC/8 01: OSC/16 10: OSC/32 11: OSC/64
1 0
MA1 MA0
1 1
R/W R/W
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Section 6 Power-Down Modes
6.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes with SYSCR1 and SYSCR3.
Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 NESEL 1 R/W Noise Elimination Sampling Frequency Select This bit selects the sampling frequency of OSC when W is sampled. When a system clock is used, clear this bit to 0.When the on-chip oscillator is selected, set this bit to 1. 0: Sampling rate is OSC/16. 1: Sampling rate is OSC/4. 3 DTON 0 R/W Direct Transfer on Flag Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY, TMA3, and LSON in SYSCR1 and bit MSON in SYSCR2. For details, see table 6.2. 2 MSON 0 R/W Medium Speed on Flag After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. 0: Operation in active (high-speed) mode 1: Operation in active (medium-speed) mode 1 0 SA1 SA0 0 0 R/W R/W Subactive Mode Clock Select 1 and 0 Select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: W/8 01: W/4 10: W/2 11: Setting prohibited
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Section 6 Power-Down Modes
6.1.3
System Control Register 3 (SYSCR3)
SYSCR3 controls the power-down modes with SYSCR1 and SYSCR2.
Bit 7 to 1 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 0 STS3 0 R/W Standby Timer Select 3 Specifies the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or watch mode to active mode or sleep mode. This bit should be specified together with the STS2 to STS0 bits in SYSCR1 according to the operating frequency so that the wait time is at least equal to the oscillation stabilization time. The relationship between the specified value and the number of wait states is shown in table 6.1. When an external clock is to be used, the minimum value (STS3 = 0, STS2 = 1, STS1 = 0, STS0 = 1) is recommended. When the on-chip oscillator for the system clock is to be used, four states (STS3 = 1, STS2 = 1, STS1 = 0, STS0 = 1) is recommended. If a setting other than the recommended value is made, operation may start before the end of the wait time.
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Section 6 Power-Down Modes
Table 6.1
Bit
Operating Frequency and Wait Time
Number of Wait States 8,192 states 16,384 states 1,024 states 2,048 states 4,096 states 2 states (external clock input) 10 MHz 819.2 1,638.4 102.4 204.8 409.6 0.2 8 MHz 1,024.0 2,048.0 128.0 256.0 512.0 0.3 Operating Frequency and Wait Time 6 MHz 1,365.3 2,730.7 170.7 341.3 682.7 0.3 5 MHz 1,638.4 3,276.8 204.8 409.6 819.2 0.4 4.194 MHz 3 MHz 1,953.3 3,906.5 244.2 488.3 976.6 0.5 2,730.7 5,461.3 341.3 682.7 1,365.3 0.7 2 MHz 4,096.0 8,192.0 512.0 1,024.0 2,048.0 1.0
STS3 STS2 STS1 STS0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1
0 0 1 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1
8 states 16 states 256 states 512 states 32,768 states 65,536 states
0.8 1.6 25.6 51.2 3,276.8 6,553.6
1.0 2.0 32.0 64.0 4,096.0 8,192.0 16,384.0 0.5 4.0 16.0
1.3 2.7 42.7 85.3 5,461.3 10,922.7 21,845.3 0.7 5.3 21.3
1.6 3.2 51.2 102.4 6,553.6 13,107.2 26,214.4 0.8 6.4 25.6
1.9 3.8 61.0 122.1 7,813.1 15,626.1 31,252.3 1.0 7.6 30.5
2.7 5.3 85.3 170.7 10,922.7 21,845.3 43,690.7 1.3 10.7 42.7
4.0 8.0 128.0 256.0 16,384.0 32,768.0 65,536.0 2.0 16.0 64.0
131,072 states 13,107.2 4 states 32 states 128 states 0.4 3.2 12.8
Note: Time unit is s. When an external clock is input, bits STS3 to STS0 should be set as external clock input mode before mode transition is executed. When an external clock is not used, these bits should not be set as external clock input mode.
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Section 6 Power-Down Modes
6.1.4
Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3)
CKSTPR1, CKSTPR2, and CKSTPR3 allow the on-chip peripheral modules to enter the standby state in module units. * CKSTPR1
Bit 7 Bit Name
13
Initial Value R/W R/W
Description SCI4 Module Standby The SCI4 enters standby mode when this bit is cleared to 0.
S4CKSTP* * 1
6
S31CKSTP
1
R/W
SCI3_1 Module Standby*
2
The SCI3_1 enters standby mode when this bit is cleared to 0. 5 S32CKSTP 1 R/W SCI3_2 Module Standby*
2
The SCI3_2 enters standby mode when this bit is cleared 1 to 0.* 4 ADCKSTP 1 R/W A/D Converter Module Standby The A/D converter enters standby mode when this bit is cleared to 0. 3 2 1 -- TFCKSTP FROMCK 13 STP* * 1 1 1 R/W R/W R/W Reserved This bit can be read from or written to. Timer F Module Standby Timer F enters standby mode when this bit is cleared to 0. Flash Memory Module Standby Flash memory enters standby mode when this bit is cleared to 0. When the addresses H'000000 to H'0000FF of the flash memory space is accessed while this bit is set to 0, the RAM emulation function is enabled and the addresses H'FFFC00 to H'FFFCFF of the RAM space can be accessed. For details, see section 7.4, Using RAM to Emulate Flash Memory. The RAM emulation function is supported only by the FZTAT version. 0 RTCCKSTP 1 R/W RTC Module Standby RTC enters standby mode when this bit is cleared to 0.
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Section 6 Power-Down Modes
* CKSTPR2
Bit 7 Bit Name ADBCKSTP Initial Value 1 R/W R/W Description Address Break Module Standby The address break enters standby mode when this bit is cleared to 0. 6 TPUCKSTP 1 R/W TPU Module Standby The TPU enters standby mode when this bit is cleared to 0. 5 IICCKSTP 1 R/W IIC2 Module Standby The IIC2 enters standby mode when this bit is cleared to 0. 4 PW2CKSTP 1 R/W PWM2 Module Standby The PWM2 enters standby mode when this bit is cleared to 0. 3 AECCKSTP 1 R/W Asynchronous Event Counter Module Standby The asynchronous event counter enters standby mode when this bit is cleared to 0. 2 WDCKSTP 1 R/W*
4
Watchdog Timer Module Standby The watchdog timer enters standby mode when this bit is cleared to 0.
1
PW1CKSTP
1
R/W
PWM1 Module Standby The PWM1 enters standby mode when this bit is cleared to 0.
0
LDCKSTP
1
R/W
LCD Module Standby The LCD controller/driver enters standby mode when this bit is cleared to 0.
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Section 6 Power-Down Modes
* CKSTPR3
Bit 7 Bit Name S33CKSTP Initial Value 1 R/W R/W Description SCI3_3 Module Standby*
2
The SCI3_3 enters standby mode when this bit is cleared to 0. 6 TCCKSTP 1 R/W Timer C Module Standby The timer C enters standby mode when this bit is cleared to 0. 5 TGCKSTP 1 R/W Timer G Module Standby The timer G enters standby mode when this bit is cleared to 0. 4 PW4CKSTP 1 R/W PWM4 Module Standby The PWM4 enters standby mode when this bit is cleared to 0. 3 PW3CKSTP 1 R/W PWM3 Module Standby The PWM3 enters standby mode when this bit is cleared to 0. 2 to 0 -- All 0 -- Reserved These bits are always read as 0 and cannot be modified. Notes: 1. 2. 3. 4. This bit is always read as 1 and cannot be modified in the masked ROM version. When the SCI3 module standby is set, all registers in the SCI3 enter the reset state. This bit must be set to 1 when the on-chip emulator is used. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0. However, the watchdog timer does not enter module standby mode and continues operating. When the WDON bit is cleared to 0 by software, this bit is valid and the watchdog timer enters module standby mode.
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Section 6 Power-Down Modes
6.2
Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. The program execution state is recovered from the program halt state by an interrupt. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. The operating frequencies can be changed in the same mode by a direct transition from active mode to active mode, or from subactive mode to subactive mode. RES input enables transitions from a mode to the reset state. Table 6.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 6.3 shows the internal states of the LSI in each mode.
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Section 6 Power-Down Modes
Reset state Program halt state Standby mode SLEEP d instruction 4 d SLEEP instruction
Program execution state Active (high-speed mode) g f SLEEP instruction 4 SLEEP instruction
SLEEP instruction a 3 a Pn EE ctio SL tru s in
Pn EE tio SL truc s in
Program halt state Sleep (high-speed) mode
b
SLEEP b instruction e SLEEP instruction 1 e
S ins LE tru EP cti on
Active (medium-speed) mode j SLEEP instruction i h SLEEP instruction SLEEP instruction i SLEEP instruction
3
Sleep (medium-speed) mode
1
Watch mode
e SLEEP instruction 1
Subactive mode
SLEEP instruction c 2
Subsleep mode
: Transition is made after exception handling is executed. Mode Transition Conditions (1) LSON a b c d e f g h i j 0 0 1 0 * 0 0 0 1 0 MSON SSBY 0 1 * * * 0 1 1 * 0 0 0 0 1 1 0 0 1 1 1 TMA3 * * 1 0 1 * * 1 1 1 DTON 0 0 0 0 0 1 1 1 1 1 * Don't care
3 4 2 1
Power-down modes Mode Transition Conditions (2) Interrupt Sources
NMI, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, RTC, WDT, AEC, Timer C, Timer F, Timer G All interrupts except for TPU, IIC2, A/D, address break interrupts All interrupts NMI, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, WDT, AEC
Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure to enable the interrupt request.
Figure 6.1 Mode Transition Diagram
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Section 6 Power-Down Modes
Table 6.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling
Transition Mode after SLEEP State Transition Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Active (highspeed) mode 0 0 0 x 0 Sleep (highspeed) mode Sleep (mediumspeed) mode Standby mode Standby mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition) Active (highspeed) mode
Symbol in Figure 6.1 a
0
1
0
x
0
Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode
b
0 0
0 1
1 1
0 0
0 0
d d
0 0
0 1
1 1
1 1
0 0
e e
1 0
x 0
1 0
1 x
0 1
Subactive mode e
0
1
0
x
1
g
1
x
1
1
1
i
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Section 6 Power-Down Modes
Transition Mode after SLEEP State Transition Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Active (mediumspeed) mode 0 0 0 x 0 Sleep (highspeed) mode Sleep (mediumspeed) mode Standby mode Standby mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition) Active (highspeed) mode
Symbol in Figure 6.1 a
0
1
0
x
0
Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode Active (highspeed) mode Active (mediumspeed) mode
b
0 0
0 1
1 1
0 0
0 0
d d
0 0
0 1
1 1
1 1
0 0
e e
1 0
1 0
1 0
1 x
0 1
Subactive mode e f
0
1
0
x
1
1
x
1
1
1
i
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Section 6 Power-Down Modes
Transition Mode after SLEEP State Transition Before Instruction Mode due to Transition LSON MSON SSBY TMA3 DTON Execution Interrupt Subactive mode 1 0 0 x 0 1 0 1 1 1 1 1 0 0 0 Subsleep mode Watch mode Watch mode Watch mode Active (highspeed) mode (direct transition) Active (mediumspeed) mode (direct transition) Subactive mode (direct transition)
Symbol in Figure 6.1
Subactive mode c Active (highspeed) mode Active (mediumspeed) mode e e
1 0
x 0
1 1
1 1
0 1
Subactive mode e j
0
1
1
1
1
h
1
x
1
1
1
[Legend] x: Don't care
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Section 6 Power-Down Modes
Table 6.3
Internal State in Each Operating Mode
Active Mode MediumHigh-speed speed Functioning Functioning Sleep Mode Mediumspeed Functioning Functioning/ halted Halted Retained Subactive Watch Mode Mode Halted Functioning Halted Retained Halted Functioning Functioning Subsleep Mode Halted Functioning Halted Retained Stand-by Mode Halted Functioning/ halted Halted Retained
Function System clock oscillator Subclock oscillator CPU Instructions RAM Registers I/O External interrupts NMI IRQ0 IRQ1 IRQ3 IRQ4 IRQAEC WKP0 to WKP7 Peripheral modules Timer C Timers F, G Asynchronous event counter RTC TPU WDT SCI3/IrDA IIC2 PWM A/D converter LCD Address break
High-speed Functioning
Functioning/ Functioning/ Functioning/ halted halted halted Functioning Functioning Halted Retained
Retained*1 Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Functioning
Functioning
Functioning
Functioning
Functioning/ retained*2 Functioning/ retained*3 Functioning Functioning/ retained*8 Retained
Functioning/ retained* Reset
4
Functioning/ Functioning/ Retained retained*2 retained*2 Functioning/ Functioning/ Retained retained*3 retained*3 Functioning Functioning Functioning
Functioning/ Functioning/ Retained retained*8 retained*8 Retained
Functioning/ retained*
4
Retained
Functioning/ retained*
4
Retained
Functioning/ retained* Reset
5
Functioning/ retained*
6
Functioning/ retained*
6
Retained
Retained
Retained
Retained
Functioning/ retained*
7
Functioning/ retained*
7
Functioning/ retained*
7
Retained
Retained
Retained
Functioning
Retained
Notes:
1. 2. 3. 4. 5. 6. 7. 8.
Register contents are retained. Output is the high-impedance state. Functioning if W/4, W/256, or W/1024 is selected as an internal clock. Halted and retained otherwise. Functioning if W/4 is selected as an internal clock. Halted and retained otherwise. Functioning if the on-chip WDT oscillator is selected or if W/16, or W/256 is selected as an internal clock. Halted and retained otherwise. Functioning if the on-chip WDT oscillator is selected. Halted and retained otherwise. Functioning if W/2 is selected as an internal clock. Halted and retained otherwise. Functioning if W, W/2, or W/4 is selected as an internal clock. Halted and retained otherwise. Functions if the RTC operation is selected as a clock source. Halted and retained for the free-running counter.
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Section 6 Power-Down Modes
6.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, on-chip oscillator for the system clock, subclock oscillator, and on-chip peripheral modules continues operating. In sleep (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed) mode to active (medium-speed) mode. When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an interrupt request signal is synchronous with the system clock, the maximum time of 2/ (s) may be delayed from the point at which an interrupt request signal occurs until the interrupt exception handling is started. 6.2.2 Standby Mode
In standby mode, the system clock oscillator and on-chip oscillator for the system clock is halted, so the CPU and on-chip peripheral modules except for WDT and asynchronous event counter stop functioning. However, as long as the rated voltage is supplied, the contents of CPU registers and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock oscillator and on-chip oscillator for the system clock start. After the time set in the STS2 to STS0 bits in SYSCR1 and the STS3 bit in SYSCR3 has elapsed, standby mode is cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made to active (highspeed) or active (medium-speed) mode according to the MSON bit in SYSCR2. Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. When a reset source is generated in standby mode, the system clock oscillator and the on-chip oscillator for the system clock start. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high.
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Section 6 Power-Down Modes
6.2.3
Watch Mode
In watch mode, the system clock oscillator, on-chip oscillator for the system clock, and CPU operation stop and on-chip peripheral modules stop functioning except for the WDT, RTC, timer C, timer F, timer G, asynchronous event counter, and LCD controller/driver. However, as long as the rated voltage is supplied, the contents of CPU registers, some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain their state before the transition. Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is made to active mode, after the time set in the STS2 to STS0 bits in SYSCR1 and the STS3 bit in SYSCR3 has elapsed, interrupt exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in watch mode, the system clock oscillator starts. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high. 6.2.4 Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules other than the TPU, A/D converter, PWM, IIC2, and address break continue running. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in subsleep mode, the system clock oscillator starts. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high.
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Section 6 Power-Down Modes
6.2.5
Subactive Mode
In subactive mode, the system clock oscillator and the on-chip oscillator for the system clock stop functioning but on-chip peripheral modules other than the A/D converter, PWM, TPU, and IIC2 continue to operate. As long as a required voltage is applied, the contents of some registers of the on-chip peripheral modules are retained. Subactive mode is cleared by the SLEEP instruction. When subacitve mode is cleared, a transition to subsleep mode, active mode, or watch mode is made, depending on the combination of bits SSBY, LSON, and TMA3 in SYSCR1 and bits MSON and DTON in SYSCR2. When a reset source is generated in subactive mode, the system clock oscillator starts. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high. The operating frequency of subactive mode is selected from W/2, W/4, and W/8 by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution. 6.2.6 Active (Medium-Speed) Mode
In active (medium-speed) mode, the clock set by the MA1 and MA0 bits in SYSCR1 is used as the system clock, and the CPU and on-chip peripheral modules function. Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combination of bits SSBY, LSON, and TMA3 in SYSCR1, a transition to watch mode is made depending on the combination of bits SSBY and TMA3 in SYSCR1, or a transition to sleep mode is made depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. When a reset source is generated in active (medium-speed) mode, the CPU goes into the reset state and active (mediumsleep) mode is cleared.
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Section 6 Power-Down Modes
6.3
Direct Transition
The CPU can execute programs in two modes: active and subactive modes. A direct transition is made between these two modes without stopping program execution. A direct transition can also be made when the operating clock is changed in active and subactive modes. The transition is made via the sleep or watch mode, by setting the DTON bit in SYSCR2 to 1 to execute a SLEEP instruction. After the mode transition, direct transition interrupt exception handling starts. Note that if a direct transition is attempted while the I bit in CCR is 1, the transition is made to the sleep or watch mode, though not returning from the mode. 6.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made to active (medium-speed) mode via sleep mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tcyc after transition) ... ......(1) Example: When osc/8 is selected as the CPU operating clock after the transition Direct transition time = (2 + 1) x 1tosc + 14 x 8tosc = 115tosc For the legend of symbols used above, refer to section 26, Electrical Characteristics.
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Section 6 Power-Down Modes
6.3.2
Direct Transition from Active (High-Speed) Mode to Subactive Mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY, TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tsubcyc after transition) ......(2) Example: When w/8 is selected as the subactive operating clock after the transition Direct transition time = (2 + 1) x 1tosc + 14 x 8tw = 3tosc + 112tw For the legend of symbols used above, refer to section 26, Electrical Characteristics. 6.3.3 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tcyc after transition) ...........(3) Example: When osc/8 is selected as the CPU operating clock before the transition Direct transition time = (2 + 1) x 8tosc + 14 x 1tosc = 38tosc For the legend of symbols used above, refer to section 26, Electrical Characteristics.
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Section 6 Power-Down Modes
6.3.4
Direct Transition from Active (Medium-Speed) Mode to Subactive Mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY, LSON, and TMA3 bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tsubcyc after transition) ......(4) Example: When osc/8 and w/8 are selected as the CPU operating clock before and after the transition, respectively Direct transition time = (2 + 1) x 8tosc + 14 x 8tw = 24tosc + 112tw For the legend of symbols used above, refer to section 26, Electrical Characteristics. 6.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active (highspeed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (5). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + (Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states) x (tcyc after transition) ...............................................(5) Example: When w/8 is selected as the CPU operating clock after the transition and wait time = 8192 states Direct transition time = (2 + 1) x 8tw + (8192 + 14) x 1tosc = 24tw + 8206tosc For the legend of symbols used above, refer to section 26, Electrical Characteristics.
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Section 6 Power-Down Modes
6.3.6
Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (6). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + (Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states) x (tcyc after transition) ...............................................(6) Example: When w/8 and osc/8 are selected as the CPU operating clock before and after the transition, respectively, and wait time = 8192 states Direct transition time = (2 + 1) x 8tw + 8192 x 1tosc + 14 x 8tosc = 24tw + 8304tosc For the legend of symbols used above, refer to section 26, Electrical Characteristics.
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Section 6 Power-Down Modes
6.3.7 (1)
Notes on External Input Signal Changes before/after Direct Transition Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode. (2) Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode. (3) Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode. (4) Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see section 6.5.2, Notes on External Input Signal Changes before/after Standby Mode.
6.4
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the clock supply to modules stops to enter the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each module in CKSTPR1 to CKSTPR3 and cancels the mode by setting the bit to 1 (see section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3)).
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Section 6 Power-Down Modes
6.5
6.5.1
Usage Notes
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while the SSBY and TMA3 bits in SYSCR1 are set to 1 and the LSON bit in SYSCR1 is cleared to 0, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 6.2 shows the timing in this case.
Internal data bus
SLEEP instruction fetch
Next instruction fetch Internal processing High-impedance Standby mode
SLEEP instruction execution Pins Port output
Active (high-speed) mode or active (medium-speed) mode
Figure 6.2 Standby Mode Transition and Pin States
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Section 6 Power-Down Modes
6.5.2 (1)
Notes on External Input Signal Changes before/after Standby Mode When External Input Signal Changes before/after Standby Mode or Watch Mode
When an external input signal such as NMI, IRQ, WKP, or IRQAEC is input, both the high- and low-level widths of the signal must be at least two cycles of system clock or subclock SUB (referred to together in this section as the internal clock). As the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. Ensure that external input signals conform to the conditions stated in (3), Recommended Timing of External Input Signals, below. (2) When External Input Signals cannot be Captured because Internal Clock Stops
The case of falling edge capture is shown in figure 6.3. As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc. (3) Recommended Timing of External Input Signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "Capture possible: case 1." External input signal capture is also possible with the timing shown in "Capture possible: case 2" and "Capture possible: case 3," in which a 2 tyc or 2 tsubcyc level width is secured.
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Section 6 Power-Down Modes
Active (high-speed, medium-speed) Operating mode mode or subactive mode tcyc tsubcyc or SUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible tcyc tsubcyc
Standby mode or watch mode tcyc tsubcyc
Wait for oscActive (high-speed, medium-speed) illation mode or subactive mode stabilization tcyc tsubcyc
Interrupt by different signal
Figure 6.3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode (4) Input Pins to which these Notes Apply
NMI, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG, TIOCA1, TIOCB1, TIOCA2, and TIOCB2.
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Section 7 ROM
Section 7 ROM
The features of the 128-Kbyte flash memory built into the flash memory (F-ZTAT) version are summarized below. * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 Kbyte x 4 blocks, 28 Kbytes x 1 block, 16 Kbytes x 1 block, 8 Kbytes x 2 blocks, and 32 Kbytes x 2 blocks. To erase the entire flash memory, each block must be erased in turn. * On-board programming On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing. * Power-down mode Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash memory can be read with low power consumption. * Module standby mode Use of module standby mode enables this module to be placed in standby mode independently when not used (for details, see section 6.4, Module Standby Function). When the on-chip debugger is in use, the bit 1 (FROMCKSTP) in the clock stop register 1 (CKSTPR1) must be set to 1.
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Section 7 ROM
7.1
Block Configuration
Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 128-Kbyte flash memory is divided into 1 Kbyte x 4 blocks, 28 Kbytes x 1 block, 16 Kbytes x 1 block, 8 Kbytes x 2 blocks, and 32 Kbytes x 2 blocks . Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
EB0 Erase unit 1 Kbyte EB1 Erase unit 1 Kbyte EB2 Erase unit 1 Kbyte EB3 Erase unit 1 Kbyte EB4 Erase unit 28 Kbytes EB5 Erase unit 16 Kbytes EB6 Erase unit 8 Kbytes EB7 Erase unit 8 Kbytes EB8 Erase unit 32 Kbytes EB9 Erase unit 32 Kbytes
H'000000 H'000380 H'000400
H'000001 H'000381 H'000401
H'000002 H'000382 H'000402
Programming unit: 128 bytes
H'00007F H'0003FF
Programming unit: 128 bytes
H'00047F
H'000780 H'000800
H'000781 H'000801
H'000782 H'000802 Programming unit: 128 bytes
H'0007FF H'00087F
H'000B80 H'000C00
H'000B81 H'000C01
H'000B82 H'000C02 Programming unit: 128 bytes
H'000BFF H'000C7F
H'000F80 H'001000 H'007F80 H'008000 H'00BF80 H'00C000 H'00DF80 H'00E000 H'00FF80 H'010000 H'017F80 H'018000 H'01FF80
H'000F81 H'001001 H'007F81 H'008001 H'00BF81 H'00C001 H'00DF81 H'00E001 H'00FF81 H'010001 H'017F81 H'018001 H'01FF81
H'000F82 H'001002 H'007F82 H'008002 H'00BF82 H'00C002 H'00DF82 H'00E002 H'00FF82 H'010002 H'017F82 H'018002 H'01FF82 Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes Programming unit: 128 bytes
H'000FFF H'00107F H'007FFF H'00807F H'00BFFF H'00C07F H'00DFFF H'00E07F H'00FFFF H'01007F H'017FFF H'01807F H'01FFFF
Figure 7.1 Flash Memory Block Configuration
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Section 7 ROM
7.2
Register Descriptions
The flash memory has the following registers. * Flash memory control register 1 (FLMCR1) * Flash memory control register 2 (FLMCR2) * Erase block register 1 (EBR1) * Erase block register 2 (EBR2) * Flash memory power control register (FLPWCR) * Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.5, Flash Memory Programming/Erasing.
Bit 7 6 Bit Name SWE Initial Value 0 0 R/W R/W Description Reserved This bit is always read as 0. Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit to 1 in FLMCR1. 4 PSU 0 R/W Program Setup When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1.
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Section 7 ROM
Bit 3
Bit Name EV
Initial Value 0
R/W R/W
Description Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled.
2
PV
0
R/W
Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled.
1
E
0
R/W
Erase When this bit is set to 1 while SWE=1 and ESU=1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled.
0
P
0
R/W
Program When this bit is set to 1 while SWE=1 and PSU=1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled.
7.2.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. See section 7.6.3, Error Protection, for details. 6 to 0 All 0 Reserved These bits are always read as 0.
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Section 7 ROM
7.2.3
Erase Block Register 1 (EBR1)
EBR1 is a register that is used to specify the flash memory erase area block. EBR1 is initialized to H'00 when the SWE1 bit in FLMCR1 is 0. Do not set more than one bit in EBR1 and EBR2 to 1 at a time, or this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
Bit 7 6 5 4 3 2 1 0 Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 8 Kbytes of EB7 (H'00E000 to H'00FFFF) will be erased. When this bit is set to 1, 8 Kbytes of EB6 (H'00C000 to H'00DFFF) will be erased. When this bit is set to 1, 16 Kbytes of EB5 (H'008000 to H'00BFFF) will be erased. When this bit is set to 1, 28 Kbytes of EB4 (H'001000 to H'007FFF) will be erased. When this bit is set to 1, 1 Kbyte of EB3 (H'000C00 to H'000FFF) will be erased. When this bit is set to 1, 1 Kbyte of EB2 (H'000800 to H'000BFF) will be erased. When this bit is set to 1, 1 Kbyte of EB1 (H'000400 to H'0007FF) will be erased. When this bit is set to 1, 1 Kbyte of EB0 (H'000000 to H'0003FF) will be erased.
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Section 7 ROM
7.2.4
Erase Block Register 2 (EBR2)
EBR2 is a register that is used to specify the flash memory erase area block. EBR2 is initialized to H'00 when the SWE1 bit in FLMCR1 is 0. Do not set more than one bit in EBR1 and EBR2 to 1 at a time, or this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
Bit 7 to 2 1 0 Bit Name EB9 EB8 Initial Value All 0 0 0 R/W R/(W) R/W R/W Description Reserved The initial value should not be changed. When this bit is set to 1, 32 Kbytes of EB9 (H'018000 to H'01FFFF) will be erased. When this bit is set to 1, 32 Kbytes of EB8 (H'010000 to H'017FFF) will be erased.
7.2.5
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Bit 7 Bit Name PDWND Initial Value 0 R/W R/W Description Power-Down Disable When this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. When this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 All 0 Reserved These bits are always read as 0.
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Section 7 ROM
7.2.6
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, EBR2, and FLPWCR.
Bit 7 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 All 0 Reserved These bits are always read as 0.
7.3
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level of each pin must be defined four states before the reset ends. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3 (channel 1). After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user.
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Section 7 ROM
Table 7.1
TEST 0 0 1
Setting Programming Modes
NMI 1 0 x P36 x 1 x PB0 x x 0 PB1 x x 0 PB2 x x 0 LSI State after Reset End User mode Boot mode Programmer mode
[Legend] x: Don't care
7.3.1
Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.5, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. The inversion function of TXD and RXD pins by SPCR is set to "Not to be inverted," so do not put the circuit for inverting a value between the host and this LSI. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 7.3. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFF380 to H'FFFE7F is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program.
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Section 7 ROM
6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of program data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the NMI pin. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the TEST pin and NMI pin input levels in boot mode.
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Section 7 ROM
Table 7.2
Item
Boot Mode Operation
Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program at reset-start.
Boot mode initiation
Boot program initiation
Bit rate adjustment
Continuously transmits data H'00 at specified bit rate.
H'00, H'00 . . . H'00
Transmits data H'55 when data H'00 is received error-free.
H'00
* Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end indication. H'55 reception.
H'55
Flash memory erase
Boot program erase error
H'FF
H'AA reception
H'AA
Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.)
Transfer of number of bytes of programming control program
Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte)
Upper bytes, lower bytes Echoback
Echobacks the 2-byte data received to host.
Transmits 1-byte of programming control program (repeated for N times)
H'XX Echoback
Echobacks received data to host and also transfers it to RAM. (repeated for N times)
H'AA reception
H'AA
Transmits data H'AA to host.
Branches to programming control program transferred to on-chip RAM and starts execution.
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Section 7 ROM
Table 7.3
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible
System Clock Frequency Range of LSI 8 to 10 MHz 4 to 10 MHz 2 to 10 MHz
Host Bit Rate 9,600 bps 4,800 bps 2,400 bps
7.3.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 7.5, Flash Memory Programming/Erasing.
Reset-start
No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program
Branch to user program/erase control program in RAM
Execute user program/erase control program (flash memory rewrite)
Branch to flash memory application program
Figure 7.2 Sample Flowchart of Programming/Erasing in User Program Mode
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Section 7 ROM
7.4
Using RAM to Emulate Flash Memory
To use on-chip RAM in the realtime emulation of data to be written to the flash memory, the onchip RAM area can be overlaid on several blocks of flash memory (the emulation area). Figure 7.3 shows an example where an area of on-chip RAM is overlaid on the emulation area of the flash memory. 1. The area of on-chip RAM area to be overlaid on the emulation area (i.e. the overlay RAM area) is fixed to the 256 bytes from H'FFFC00 to H'FFFCFF. 2. The block of flash memory on which the RAM can be overlaid (i.e. the emulation area) takes up the 256 bytes from H'000000 to H'0000FF. 3. When the FROMCKSTP bit in CKSTPR1 is cleared to 0, the flash memory enters standby mode. The overlay RAM area is overlaid on the emulation area and becomes the target for access when the emulation area of the flash memory is accessed. 4. The overlay RAM area can be accessed at both the addresses within the flash memory area and the original RAM addresses. When using RAM emulation, a vector table is required for the overlaid RAM area. 5. Overlaying of the on-chip RAM is canceled when the FROMCKSTP bit in CKSTPR1 is set, taking the flash memory out of standby mode. This should only be done after execution has made the transition from the emulation area to the RAM area.
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Section 7 ROM
H'000000
Flash memory emulation area (H'000000 to H'0000FF) 256 bytes
On-chip RAM (shadow of H'FFFC00 to H'FFFCFF) 256 bytes
H'0000FF
Flash memory Not used
H'020000
H'FFFC00
On-chip RAM overlay area 256 bytes On-chip RAM overlay area 256 bytes
H'FFFCFF
Normal memory map
Memory map with overlaid RAM area
Figure 7.3 Address Map of Overlaid RAM Area
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Section 7 ROM
7.5
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 7.5.1, Program/Program-Verify and section 7.5.2, Erase/Erase-Verify, respectively. 7.5.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.4 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words or in longwords from the address to which a dummy write was performed.
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Section 7 ROM
8.
The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait time=programming time) Clear P bit in FLMCR1 Wait 5 s Clear PSU bit in FLMCR1 Wait 5 s Disable WDT End Sub
Write 128-byte data in RAM reprogram data area consecutively to flash memory
START Set SWE bit in FLMCR1 Wait 1 s
*
Store 128-byte program data in program data area and reprogram data area
n1 m0
Apply Write pulse Set PV bit in FLMCR1 Wait 4 s Set block start address as verify address
H'FF dummy write to verify address
nn+1
Wait 2 s Read verify data Increment address Verify data = write data? Yes n6? Yes No
No
*
m1
Additional-programming data computation
Reprogram data computation 128-byte data verification completed? Yes Clear PV bit in FLMCR1 Wait 2 s n 6? Yes No
No
Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call
Apply Write Pulse No m= 0 ? Yes Clear SWE bit in FLMCR1 Wait 100 s End of programming Note: *The RTS instruction must not be used during the following 1. and 2. periods. 1. A period between 128-byte data programming to flash memory and the P bit clearing 2. A period between dummy writing of H'FF to a verify address and verify data reading Yes n 1000 ? No Clear SWE bit in FLMCR1 Wait 100 s Programming failure
Figure 7.4 Program/Program-Verify Flowchart
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Section 7 ROM
Table 7.4
Reprogram Data Computation Table
Verify Data 0 1 0 1 Reprogram Data 1 0 1 1 Comments Programming completed Reprogram bit Remains in erased state
Program Data 0 0 1 1
Table 7.5
Additional-Program Data Computation Table
Verify Data 0 1 0 1 Additional-Program Data 0 1 1 1 Comments Additional-program bit No additional programming No additional programming No additional programming
Reprogram Data 0 0 1 1
Table 7.6
Programming Time
In Additional Programming 10 Comments
n Programming (Number of Writes) Time 1 to 6 7 to 1,000 30 200
Note: Time shown in s.
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Section 7 ROM
7.5.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.5 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1 (EBR1) or the erase block register 2 (EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 19.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.5.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
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Section 7 ROM
Erase start SWE bit 1 Wait 1 s n1 Set EBR1 Enable WDT ESU bit 1 Wait 100 s E bit 1 Wait 10 ms E bit 0 Wait 10 s ESU bit 0 10 s Disable WDT EV bit 1 Wait 20 s
Set block start address as verify address
H'FF dummy write to verify address Wait 2 s Read verify data No
*
nn+1
Increment address
Verify data = all '1'? Yes No Last address of block ? Yes EV bit 0 Wait 4 s
EV bit 0 Wait 4s
No
All erase block erased ? Yes SWE bit 0 Wait 100 s End of erasing
n 100 ? No SWE bit 0 Wait 100 s Erase failure
Yes
Note: * The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.5 Erase/Erase-Verify Flowchart
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Section 7 ROM
7.6
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.6.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 7.6.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1) or the erase block register 2 (EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. 7.6.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling excluding a reset during programming/erasing * When a SLEEP instruction is executed during programming/erasing
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Section 7 ROM
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a reset.
7.7
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip 128-Kbyte flash memory (FZTAT128V3).
7.8
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to at high speed. * Power-down operating mode The power supply circuit of flash memory can be partly halted. As a result, flash memory can be read with low power consumption. * Standby mode All flash memory circuits are halted. Table 7.7 shows the correspondence between the operating modes of this LSI and the flash memory. In subactive mode, the flash memory can be set to operate in power-down mode with the PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS3 to STS0 in SYSCR1 and SYSCR3 must be set to provide a wait time of at least 20 s, even when the external clock is in use.
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Section 7 ROM
Table 7.7
Flash Memory Operating States
Flash Memory Operating State
LSI Operating State Active mode Sleep mode Subactive mode Subsleep mode Module standby mode* Standby mode Note: *
PDWND = 0 (Initial Value) Normal operating mode Normal operating mode Power-down mode Standby mode Standby mode Standby mode
PDWND = 1 Normal operating mode Normal operating mode Normal operating mode Standby mode Standby mode Standby mode
When the flash memory returns to its normal operating state, a wait time of not less than 100 s is required.
7.9
Notes on Setting Module Standby Mode
When the flash memory is set to enter module standby mode, the system clock supply is stopped to the module, the function is stopped, and the state is the same as that in standby mode. Also program operation is stopped in the flash memory. Therefore operation program should be transferred to the RAM and the program should run in the RAM. Then the flash memory should be set to enter module standby mode. When the RAM emulation is not in use, if an interrupt is generated in module standby mode, the vector address cannot be fetched. As a result, the program may run away. Before the flash memory is set to enter module standby mode, the corresponding bit in the interrupt enable register should be cleared to 0 and the I bit in CCR should be set to 1. Then after the flash memory enters module standby mode, NMI and address break interrupt requests should not be generated. Figure 7.6 shows a module standby mode setting when the RAM emulation is not used.
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Section 7 ROM
Transfer execution program to RAM (user area)
Clear corresponding bit in interrupt enable register to 0
Set I bit in CCR to 1
Jump to address of execution program in RAM
Clear FROMCKSTP bit in CRSTPR1 to 0
Figure 7.6 Module Standby Mode Setting when RAM Emulation is not Used When the RAM emulation is used (an interrupt vector is provided), if an interrupt is generated in module standby mode, the vector address can be set by assigning the interrupt vector to the RAM, and this prevents the program to run away. For details, see section 7.4, Using RAM to Emulate Flash Memory.
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Section 8 RAM
Section 8 RAM
Microcontrollers of the H8/38099 Group include an on-chip high-speed static RAM. The RAM is connected to the CPU via a 16-bit data bus, enabling two-cycle access by the CPU to both byte and word data.
Product Classification Flash memory version Masked ROM version RAM Size H8/38099F 4 Kbytes H8/38099 H8/38098 4 Kbytes 2 Kbytes RAM Address Ranges H'FFCF80 to H'FFD37F, H'FFF380 to H'FFFF7F H'FFCF80 to H'FFD37F, H'FFF380 to H'FFFF7F H'FFF780 to H'FFFF7F
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Section 8 RAM
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Section 9 I/O Ports
Section 9 I/O Ports
Microcontrollers of the H8/38099 Group incorporate 75 general I/O ports and eight general inputonly ports. Port 9 is a large current port, which can drive 15 mA (@VOL = 1.0 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. The registers for selecting these functions can be divided into two types: those included in I/O ports and those included in each onchip peripheral module. General I/O ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. For details on the execution of bit manipulation instructions to the port data register (PDR), see section 2.8.3, Bit-Manipulation Instruction. For details on block diagrams for each port, see appendix B.1, I/O Port Block Diagrams.
9.1
Port 1
Port 1 is an I/O port; its pins can also be configured to function as an SCI4 I/O pin, TPU I/O pins, and asynchronous event counter input pins. Figure 9.1 shows the pin configuration.
P16/SCK4 P15/TIOCB2
Port 1
P14/TIOCA2/TCLKC P13/TIOCB1/TCLKB P12/TIOCA1/TCLKA P11/AEVL P10/AEVH
Figure 9.1 Port 1 Pin Configuration Port 1 has the following registers. * Port data register 1 (PDR1) * Port control register 1 (PCR1) * Port pull-up control register 1 (PUCR1) * Port mode register 1 (PMR1)
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Section 9 I/O Ports
9.1.1
Port Data Register 1 (PDR1)
PDR1 is a register that stores data of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name P16 P15 P14 P13 P12 P11 P10 Initial Value 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved This bit is always read as 1 and cannot be modified. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
9.1.2
Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 Initial Value 1 0 0 0 0 0 0 0 R/W W W W W W W W Description Reserved This bit is always read as 1 and cannot be modified. Setting a PCR1 bit to 1 makes the corresponding pin (P16 to P10) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid when the corresponding pin is designated as a general I/O pin. PCR1 is a write-only register. These bits are always read as 1.
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Section 9 I/O Ports
9.1.3
Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS of the port 1 pins in bit units.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 Initial Value 1 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved This bit is always read as 1 and cannot be modified. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
9.1.4
Port Mode Register 1 (PMR1)
PMR1 controls the selection of functions for port 1 pins.
Bit 7 to 2 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 1 AEVL 0 R/W P11/AEVL Pin Function Switch Selects whether pin P11/AEVL is used as P11 or as AEVL. 0: P11 I/O pin 1: AEVL input pin 0 AEVH 0 R/W P10/AEVH Pin Function Switch Selects whether pin P10/AEVH is used as P10 or as AEVH. 0: P10 I/O pin 1: AEVH input pin
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Section 9 I/O Ports
9.1.5
Pin Functions
The relationship between the register settings and the port functions is shown below. * P16/SCK4 pin
Register Name Bit Name Setting Value CKS3* 1*
1 1
SCSR4*
1 1 1
PCR1 PCR16 0 1
Pin Function
CKS2 to CKS0*
Other than B'111*
1
P16 input pin P16 output pin SCK4 input pin*
2 2
B'111* 0*
1
x x
x*
1
SCK4 output pin*
[Legend] x: Don't care TM Notes: 1. Supported only by the F-ZTAT version. 2. Only port function is available for the masked ROM version.
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Section 9 I/O Ports
* P15/TIOCB2 pin
Register Name Bit Name Setting Value TMDR_2 MD1, MD0 B'00 TIOR_2 IOB3 to IOB0 B'0x00 TCR_2 CCLR1, CCLR0 B'xx PCR1 PCR15 0 1 B'1xxx 0 1 B'0001 to B'0011, B'0101 to B'0111 B'01 B'xxxx x 0 1 B'10 0 1 B'11 B'xx00 0 1 Other than B'xx00 B'10 0 1 Other than B'10 x P15 input pin P15 output pin P15 input/TIOCB2 input pin P15 output/TIOCB2 input pin TIOCB2 output pin P15 input pin P15 output pin P15 input pin P15 output pin P15 input pin P15 output pin P15 input pin P15 output pin TIOCB2 output pin Pin Function
[Legend] x: Don't care
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Section 9 I/O Ports
* P14/TIOCA2/TCLKC pin
Register Name Bit Name Setting Value TMDR_2 MD1, MD0 B'00 TIOR_2 IOA3 to IOA0 B'0x00 TCR_2 CCLR1, CCLR0 B'xx PCR1 PCR14 0 1 B'1xxx 0 1 B'0001 to B'0011, B'0101 to B'0111 B'01 B'xxxx x 0 1 B'10 B'xx00 0 1 Other than B'xx00 B'11 B'xx00 x 0 1 Other than B'xx00 B'01 0 1 Other than B'01 x P14 input pin/ TCLKC*1 input pin P14 output pin/ TCLKC*1 input pin P14 input pin/TIOCA2/ TCLKC*1 input pin P14 output pin/TIOCA2/ TCLKC*1 input pin TIOCA2 output pin*2/ TCLKC*1 input pin P14 input pin/TCLKC*1 input pin P14 output pin/TCLKC*1 input pin P14 input pin/TCLKC*1 input pin P14 output pin/TCLKC*1 input pin TIOCA2 output pin*2/ TCLKC*1 input pin P14 input pin/TCLKC*1 input pin P14 output pin/TCLKC*1 input pin P14 input pin/TCLKC*1 input pin P14 output pin/TCLKC*1 input pin TIOCA2 output pin/ TCLKC*1 input pin Pin Function
[Legend] x: Don't care Notes: 1. When the TPSC2 to TPSC0 bits in TCR_2 are set to B'110, the pin function becomes the TCLKC input pin. 2. The output of the TIOCB2 pin is disabled.
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Section 9 I/O Ports
* P13/TIOCB1/TCLKB pin
Register Name Bit Name Setting Value TMDR_1 MD1, MD0 B'00 TIOR_1 IOB3 to IOB0 B'0x00 TCR_1 CCLR1, CCLR0 B'xx PCR1 PCR13 0 1 B'1xxx 0 1 B'0001 to B'0011, B'0101 to B'0111 B'01 B'xxxx x P13 input pin/TCLKB* input pin P13 output pin/TCLKB* input pin P13 input pin/TIOCB1/TCLKB* input pin P13 output pin/TIOCB1/TCLKB* input pin TIOCB1 output pin/TCLKB* input pin Pin Function
0 1
P13 input pin/TCLKB* input pin P13 output pin/TCLKB* input pin P13 input pin/TCLKB* input pin P13 output pin/TCLKB* input pin P13 input pin/TCLKB* input pin P13 output pin/TCLKB* input pin P13 input pin/TCLKB* input pin P13 output pin/TCLKB* input pin TIOCB1 output pin/TCLKB* input pin
B'10
0 1
B'11
B'xx00
0 1
Other than B'xx00
B'10
0 1
Other than B'10
x
[Legend] x: Don't care Note: * When the TPSC2 to TPSC0 bits in either TCR_1 or TCR_2 are set to B'101, the pin function becomes the TCLKB input pin.
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Section 9 I/O Ports
* P12/TIOCA1/TCLKA pin
Register Name Bit Name Setting Value TMDR_1 MD1, MD0 B'00 TIOR_1 IOA3 to IOA0 B'0x00 TCR_1 CCLR1, CCLR0 B'xx PCR1 PCR12 0 1 B'1xxx 0 1 B'0001 to B'0011, B'0101 to B'0111 B'01 B'xxxx x P12 input pin/TCLKA*1 input pin P12 output pin/TCLKA*1 input pin P12 input pin/TIOCA1/TCLKA*1 input pin P12 output pin/TIOCA1/TCLKA*1 input pin TIOCA1 output pin*2/TCLKA*1 input pin Pin Function
0 1
P12 input pin/TCLKA*1 input pin P12 output pin/TCLKA*1 input pin P12 input pin/TCLKA*1 input pin P12 output pin/TCLKA*1 input pin TIOCA1 output pin*2/TCLKA*1 input pin P12 input pin/TCLKA*1 input pin P12 output pin/TCLKA*1 input pin P12 input pin/TCLKA*1 input pin P12 output pin/TCLKA*1 input pin TIOCA1 output pin/TCLKA*1 input pin
B'10
B'xx00
0 1
Other than B'xx00 B'11 B'xx00
x 0 1
Other than B'xx00
B'01
0 1
Other than B'01
x
[Legend] x: Don't care Notes: 1. When the TPSC2 to TPSC0 bits in either TCR_1 or TCR_2 are set to B'100, the pin function becomes the TCLKA input pin. 2. The output of the TIOCB1 pin is disabled.
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Section 9 I/O Ports
* P11/AEVL pin
Register Name Bit Name Setting Value PMR1 AEVL 0 PCR1 PCR11 0 1 1 [Legend] x: Don't care x P11 input pin P11 output pin AEVL input pin Pin Function
* P10/AEVH pin
Register Name Bit Name Setting Value PMR1 AEVH 0 PCR1 PCR10 0 1 1 [Legend] x: Don't care x P10 input pin P10 output pin AEVH input pin Pin Function
9.1.6
Input Pull-Up MOS
Port 1 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 6 to 0) PCR1n PUCR1n Input Pull-Up MOS [Legend] x: Don't care 0 Off 0 1 On 1 x Off
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Section 9 I/O Ports
9.2
Port 3
Port 3 is an I/O port; its pins can also be configured to function as an SCI4 I/O pin, SCI3_2 I/O pin, IIC2 I/O pin, and RTC output pin. Figure 9.2 shows the pin configuration.
P37/SO4 P36/SI4
Port 3
P32/TXD32/SCL P31/RXD32/SDA P30/SCK32/TMOW/CLKOUT
Figure 9.2 Port 3 Pin Configuration Port 3 has the following registers. * Port data register 3 (PDR3) * Port control register 3 (PCR3) * Port pull-up control register 3 (PUCR3) * Port mode register 3 (PMR3) 9.2.1 Port Data Register 3 (PDR3)
PDR3 is a register that stores data of port 3.
Bit 7 6 Bit Name P37 P36 Initial Value 0 0 R/W R/W R/W Description If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read. Reserved These bits are always read as 1 and cannot be modified. 2 1 0 P32 P31 P30 0 0 0 R/W R/W R/W If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
5 to 3
All 1
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Section 9 I/O Ports
9.2.2
Port Control Register 3 (PCR3)
PCR3 selects inputs/outputs in bit units for pins of port 3.
Bit 7 6 Bit Name PCR37 PCR36 Initial Value 0 0 R/W W W Description Setting a PCR3 bit to 1 makes the corresponding pin (P37 or P36) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid when the corresponding pin is designated as a general I/O pin. PCR3 is a write-only register. These bits are always read as 1. 5 to 3 All 1 Reserved These bits are always read as 1 and cannot be modified. 2 1 0 PCR32 PCR31 PCR30 0 0 0 W W W Setting a PCR3 bit to 1 makes the corresponding pins (P32 to P30) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid when the corresponding pin is designated as a general I/O pin. PCR3 is a write-only register. These bits are always read as 1.
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Section 9 I/O Ports
9.2.3
Port Pull-Up Control Register 3 (PUCR3)
PUCR3 controls the pull-up MOS of port 3 pins in bit units.
Bit 7 6 Bit Name PUCR37 PUCR36 Initial Value 0 0 R/W R/W R/W Description When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. Reserved These bits are always read as 1 and cannot be modified. 0 PUCR30 0 R/W When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
5 to 1
All 1
9.2.4
Port Mode Register 3 (PMR3)
PMR3 controls the selection of functions for port 3 pins.
Bit 7 to 1 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 0 TMOW 0 R/W P30/SCK32/TMOW/CLKOUT Pin Function Switch Selects whether pin P30/SCK32/TMOW/CLKOUT is used as P30/SCK32 or as TMOW/CLKOUT. 0: P30/SCK32 I/O pin 1: TMOW/CLKOUT output pin
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Section 9 I/O Ports
9.2.5
Pin Functions
The relationship between the register settings and the port functions is shown below. * P37/SO4 pin
Register Name Bit Name Setting Value SCR4* TE* 0*
1 1 1
PCR3 PCR37 0 1
Pin Function
P37 input pin P37 output pin SO4 output pin*
2
1*
1
x
[Legend] x: Don't care TM Notes: 1. Supported only by the F-ZTAT version. 2. Only port function is available for the masked ROM version.
* P36/SI4 pin
Register Name Bit Name Setting Value SCR4* RE* 0*
1 1 1
PCR3 PCR36 0 1
Pin Function
P36 input pin P36 output pin SI4 input pin*
2
1*
1
x
[Legend] x: Don't care TM Notes: 1. Supported only by the F-ZTAT version. 2. Only port function is available for the masked ROM version.
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Section 9 I/O Ports
* P32/TXD32/SCL pin
Register Name Bit Name Setting Value ICCR1 ICE 0 PFCR SC32S 0 SPCR SPC32 0 PCR3 PCR32 0 1 1 1 x x 0 1 1 [Legend] x: Don't care x x P32 input pin P32 output pin TXD32 output pin P32 input pin P32 output pin SCL I/O pin Pin Function
* P31/RXD32/SDA pin
Register Name Bit Name Setting Value ICCR1 ICE 0 PFCR SC32S 0 SCR3_2 RE 0 PCR3 PCR31 0 1 1 1 x x 0 1 1 [Legend] x: Don't care x x P31 input pin P31 output pin RXD32 input pin P31 input pin P31 output pin SDA I/O pin Pin Function
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Section 9 I/O Ports
* P30/SCK32/TMOW/CLKOUT pin
Register Name Bit Name Setting Value 1 1 0 1 1 0 0 1 1 0 1 1 x x x 0 1 1 0 0 1 1 0 1 x x TMOW 0 CLKOUT1 CLKOUT0 x x SC32S 0 COM 0 CKE1 0 CKE0 0 PCR30 0 1 x P30 input pin P30 output pin SCK32 output pin SCK32 input pin Setting prohibited SCK32 output pin Setting prohibited SCK32 input pin Setting prohibited P30 input pin P30 output pin CLKOUT output pin (OSC) CLKOUT output pin (OSC/2) CLKOUT output pin (OSC/4) TMOW output pin PMR3 PFCR SMR3_2 SCR3_2 PCR3 Pin Function
[Legend] x: Don't care
9.2.6
Input Pull-Up MOS
Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7, 6, 0) PCR3n PUCR3n Input Pull-Up MOS [Legend] x: Don't care 0 Off 0 1 On 1 x Off
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Section 9 I/O Ports
9.3
Port 4
Port 4 is an I/O port; its pins can also be configured to function as SCI3_1 I/O pins and timer F I/O pins. Figure 9.3 shows its pin configuration.
Port 4
P42/TXD31/IrTXD/TMOFH P41/RXD31/IrRXD/TMOFL P40/SCK31/TMIF
Figure 9.3 Port 4 Pin Configuration Port 4 has the following registers. * Port data register 4 (PDR4) * Port control register 4 (PCR4) * Port mode register 4 (PMR4) 9.3.1 Port Data Register 4 (PDR4)
PDR4 is a register that stores data of port 4.
Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 1 0 P42 P41 P40 0 0 0 R/W R/W R/W If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is read while PCR4 bits are cleared to 0, the pin states are read.
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Section 9 I/O Ports
9.3.2
Port Control Register 4 (PCR4)
PCR4 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 4.
Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 1 0 PCR42 PCR41 PCR40 0 0 0 W W W Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR4 and in PDR4 are valid when the corresponding pin is designated as a general I/O pin. PCR4 is a write-only register. These bits are always read as 1.
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Section 9 I/O Ports
9.3.3
Port Mode Register 4 (PMR4)
PMR4 controls the selection of functions for port 4 pins.
Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 TMOFH 0 R/W P42/TXD31/IrTXD/TMOFH Pin Function Switch Selects whether pin P42/TXD31/IrTXD/TMOFH is used as P42 or TXD31/IrTXD, or as TMOFH. 0: P42 I/O pin or TXD31/IrTXD output pin 1: TMOFH output pin 1 TMOFL 0 R/W P41/RXD31/IrRXD/TMOFL Pin Function Switch Selects whether pin P41/RXD31/IrRXD/TMOFL is used as P41 or RXD31/IrRXD, or as TMOFL. 0: P41 I/O pin or RXD31/IrRXD input pin 1: TMOFL output pin 0 TMIF 0 R/W P40/SCK31/TMIF Pin Function Switch Selects whether pin P40/SCK31/TMIF is used as P40/SCK31 or as TMIF. 0: P40/SCK31 I/O pin 1: TMIF input pin
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Section 9 I/O Ports
9.3.4
Pin Functions
The relationship between the register settings and the port functions is shown below. * P42/TXD31/IrTXD/TMOFH pin
Register Name Bit Name Setting Value PMR4 TMOFH 0 PFCR SC31S 0 SPCR SPC31 0 IrCR IrE x PCR4 PCR42 0 1 1 0 1 1 x x 0 1 1 [Legend] x: Don't care x x x P42 input pin P42 output pin TXD31 output pin IrTXD output pin P42 input pin P42 output pin TMOFH output pin Pin Function
* P41/RXD31/IrRXD/TMOFL pin
Register Name Bit Name Setting Value PMR4 TMOFL 0 PFCR SC31S 0 SCR3_1 RE 0 IrCR IrE x PCR4 PCR41 0 1 1 0 1 1 x x 0 1 1 [Legend] x: Don't care x x x P41 input pin P41 output pin RXD31 output pin IrRXD output pin P41 input pin P41 output pin TMOFL output pin Pin Function
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* P40/SCK31/TMIF pin
Register Name Bit Name Setting Value PMR4 TMIF 0 PFCR SC31S 0 SMR3_1 COM 0 SCR3_1 CKE1 0 CKE0 0 PCR4 PCR40 0 1 1 1 0 1 1 0 0 1 1 0 1 1 x x x 0 1 1 x x x P40 input pin P40 output pin SCK31 output pin SCK31 input pin Setting prohibited SCK31 output pin Setting prohibited SCK31 input pin Setting prohibited P40 input pin P40 output pin TMIF input pin Pin Function
[Legend] x: Don't care
9.4
Port 5
Port 5 is an I/O port; its pins can also be configured to function as wakeup interrupt input pins and LCD segment output pins. Figure 9.4 shows the pin configuration.
P57/WKP7/SEG8 P56/WKP6/SEG7 P55/WKP5/SEG6
Port 5
P54/WKP4/SEG5 P53/WKP3/SEG4 P52/WKP2/SEG3 P51/WKP1/SEG2 P50/WKP0/SEG1
Figure 9.4 Port 5 Pin Configuration
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Section 9 I/O Ports
Port 5 has the following registers. * Port data register 5 (PDR5) * Port control register 5 (PCR5) * Port pull-up control register 5 (PUCR5) * Port mode register 5 (PMR5) 9.4.1 Port Data Register 5 (PDR5)
PDR5 is a register that stores data of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name P57 P56 P55 P54 P53 P52 P51 P50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
9.4.2
Port Control Register 5 (PCR5)
PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR5 and in PDR5 are valid when the corresponding pin is designated as a general I/O pin. PCR5 is a write-only register. These bits are always read as 1.
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9.4.3
Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS of the port 5 pins in bit units.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
9.4.4
Port Mode Register 5 (PMR5)
PMR5 controls the selection of functions for port 5 pins.
Bit 7 6 5 4 3 2 1 0 Bit Name WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description P5n/WKPn/SEGn+1 Pin Function Switch These bits select whether the pin is used as P5n or WKPn when the pin is not used as SEGn+1 pin. 0: P5n I/O pin 1: WKPn input pin (n = 7 to 0)
[Legend] For details on the SEGn+1 output pin, refer to section 21.3.1, LCD Port Control Register (LPCR).
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Section 9 I/O Ports
9.4.5
Pin Functions
The relationship between the register settings and the port functions is shown below. * P57/WKP7/SEG8 to P54/WKP4/SEG5 pins
(n = 7 to 4) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'000x, B'101x, B'11xx PMR5 WKPn 0 PCR5 PCR5n 0 1 1 0 1 Other than B'000x, B'101x, B'11xx [Legend] x: Don't care x x P5n input pin P5n output pin WKPn input pin Setting prohibited SEGn+1 output pin Pin Function
* P53/WKP3/SEG4 to P50/WKP0/SEG1 pins
(m = 3 to 0) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'0000, B'1001, B'101x, B'11xx PMR5 WKPm 0 PCR5 PCR5m 0 1 1 0 1 Other than B'0000, B'1001, B'101x, B'11xx [Legend] x: Don't care x x P5m input pin P5m output pin WKPm input pin Setting prohibited SEGm+1 output pin Pin Function
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9.4.6
Input Pull-Up MOS
Port 5 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 0) PCR5n PUCR5n Input Pull-Up MOS [Legend] x: Don't care 0 Off 0 1 On 1 x Off
9.5
Port 6
Port 6 is an I/O pins; its pins can also be configured to function as LCD segment output pins. Figure 9.5 shows the pin configuration.
P67/SEG16 P66/SEG15 P65/SEG14
Port 6
P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9
Figure 9.5 Port 6 Pin Configuration Port 6 has the following registers. * Port data register 6 (PDR6) * Port control register 6 (PCR6) * Port pull-up control register 6 (PUCR6)
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Section 9 I/O Ports
9.5.1
Port Data Register 6 (PDR6)
PDR6 is a register that stores data of port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
9.5.2
Port Control Register 6 (PCR6)
PCR6 selects inputs/outputs in bit units for pins of port 6.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR6 and in PDR6 are valid when the corresponding pin is designated as a general I/O pin. PCR6 is a write-only register. These bits are always read as 1.
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Section 9 I/O Ports
9.5.3
Port Pull-Up Control Register 6 (PUCR6)
PUCR6 controls the pull-up MOS of the port 6 pins in bit units.
Bit 7 6 5 4 3 2 1 0 Bit Name PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
9.5.4
Pin Functions
The relationship between the register settings and the port functions is shown below. * P67/SEG16 to P64/SEG13 pins
(n = 7 to 4) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'00xx, B'11xx PCR6 PCR6n 0 1 Other than B'00xx, B'11xx [Legend] x: Don't care x P6n input pin P6n output pin SEGn+9 output pin Pin Function
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* P63/SEG12 to P60/SEG9 pins
(m = 3 to 0) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'000x, B'0010, B'1011, B'11xx Other than B'000x, B'0010, B'1011, B'11xx [Legend] x: Don't care PCR6 PCR6m 0 1 x P6m input pin P6m output pin SEGm+9 output pin Pin Function
9.5.5
Input Pull-Up MOS
Port 6 has an on-chip input pull-up MOS function that can be controlled by software. When the PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 0) PCR6n PUCR6n Input Pull-Up MOS [Legend] x: Don't care 0 Off 0 1 On 1 x Off
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Section 9 I/O Ports
9.6
Port 7
Port 7 is an I/O pins; its pins can also be configured to function as LCD segment output pins. Figure 9.6 shows the pin configuration.
P77/SEG24 P76/SEG23 P75/SEG22
Port 7
P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17
Figure 9.6 Port 7 Pin Configuration Port 7 has the following registers. * Port data register 7 (PDR7) * Port control register 7 (PCR7) 9.6.1 Port Data Register 7 (PDR7)
PDR7 is a register that stores data of port 7.
Bit 7 6 5 4 3 2 1 0 Bit Name P77 P76 P75 P74 P73 P72 P71 P70 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
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9.6.2
Port Control Register 7 (PCR7)
PCR7 selects inputs/outputs in bit units for pins of port 7.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR7 and in PDR7 are valid when the corresponding pin is designated as a general I/O pin. PCR7 is a write-only register. These bits are always read as 1.
9.6.3
Pin Functions
The relationship between the register settings and the port functions is shown below. * P77/SEG24 to P74/SEG21 pins
(n = 7 to 4) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'00xx, B'010x, B'111x PCR7 PCR7n 0 1 Other than B'00xx, B'010x, B'111x [Legend] x: Don't care x P7n input pin P7n output pin SEGn+17 output pin Pin Function
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* P73/SEG20 to P70/SEG17 pins
(m = 3 to 0) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'00xx, B'0100, B'1101, B'111x Other than B'00xx, B'0100, B'1101, B'111x [Legend] x: Don't care PCR7 PCR7m 0 1 x P7m input pin P7m output pin SEGm+17 output pin Pin Function
9.7
Port 8
Port 8 is an I/O pins; its pins can also be configured to function as LCD segment output pins. Figure 9.7 shows the pin configuration.
P87/SEG32 P86/SEG31 P85/SEG30
Port 8
P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25
Figure 9.7 Port 8 Pin Configuration Port 8 has the following registers. * Port data register 8 (PDR8) * Port control register 8 (PCR8)
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Section 9 I/O Ports
9.7.1
Port Data Register 8 (PDR8)
PDR8 is a register that stores data of port 8.
Bit 7 6 5 4 3 2 1 0 Bit Name P87 P86 P85 P84 P83 P82 P81 P80 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
9.7.2
Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit 7 6 5 4 3 2 1 0 Bit Name PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCR8 bit to 1 makes the corresponding pin (P87 to P80) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR8 and in PDR8 are valid when the corresponding pin is designated as a general I/O pin. PCR8 is a write-only register. These bits are always read as 1.
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Section 9 I/O Ports
9.7.3
Pin Functions
The relationship between the register settings and the port functions is shown below. * P87/SEG32 to P84/SEG29 pins
(n = 7 to 4) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'0xxx PCR8 PCR8n 0 1 B'1xxx [Legend] x: Don't care x P8n input pin P8n output pin SEGn+25 output pin Pin Function
* P83/SEG28 to P80/SEG25 pins
(m = 3 to 0) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'00xx, B'010x, B'0110, B'1111 Other than B'00xx, B'010x, B'0110, B'1111 [Legend] x: Don't care PCR8 PCR8m 0 1 x P8m input pin P8m output pin SEGm+25 output pin Pin Function
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Section 9 I/O Ports
9.8
Port 9
Port 9 is a general I/O port; its pins can also be configured to function as an external interrupt input pin and PWM output pins. Figure 9.8 shows the pin configuration.
P93/PWM4
Port 9
P92/PWM3/IRQ4 P91/PWM2 P90/PWM1
Figure 9.8 Port 9 Pin Configuration Port 9 has the following registers. * Port data register 9 (PDR9) * Port control register 9 (PCR9) * Port mode register 9 (PMR9) 9.8.1 Port Data Register 9 (PDR9)
PDR9 is a register that stores data of port 9.
Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 2 1 0 P93 P92 P91 P90 1 1 1 1 R/W R/W R/W R/W If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read.
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Section 9 I/O Ports
9.8.2
Port Control Register 9 (PCR9)
PCR9 selects inputs/outputs in bit units for pins of port 9.
Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 2 1 0 PCR93 PCR92 PCR91 PCR90 0 0 0 0 W W W W Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and in PDR9 are valid when the corresponding pin is designated as a general I/O pin. PCR9 is a write-only register. These bits are always read as 1.
9.8.3
Port Mode Register 9 (PMR9)
PMR9 controls the selection of functions for port 9 pins.
Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 0 R/W Reserved Although this bit is readable/writable, 1 should not be written to this bit. 2 IRQ4 0 R/W P92/IRQ4 Pin Function Switch Selects whether pin P92/IRQ4 is used as P92 or as IRQ4. 0: P92 I/O pin 1: IRQ4 input pin
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Section 9 I/O Ports
Bit 1 0
Bit Name PWM2 PWM1
Initial Value 0 0
R/W R/W R/W
Description P9n/PWMn+1 Pin Function Switch Select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1. (n = 1, 0) 0: P9n I/O pin 1: PWMn+1 output pin
9.8.4
Pin Functions
The relationship between the register settings and the port functions is shown below. * P93/PWM4 pin
Register Name Bit Name Setting Value PFCR PWM4 0 PCR9 PCR93 0 1 1 [Legend] x: Don't care x P93 input pin P93 output pin PWM4 output pin Pin Function
* P92/PWM3/IRQ4 pin
Register Name Bit Name Setting Value PMR9 IRQ4 0 PFCR PMW3 0 PCR9 PCR92 0 1 1 1 [Legend] x: Don't care x x 0 1 P92 input pin P92 output pin PWM3 output pin IRQ4 input pin Setting prohibited Pin Function
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* P91/PWM2 and P90/PWM1 pins
(n = 1, 0) Register Name Bit Name Setting Value PMR9 PWMn+1 0 PCR9 PCR9n 0 1 1 [Legend] x: Don't care x P9n input pin P9n output pin PWMn+1 output pin Pin Function
9.9
Port A
Port A is an I/O pins; its pins can also be configured to function as LCD common output pins. Figure 9.9 shows the pin configuration.
PA3/COM4
Port A
PA2/COM3 PA1/COM2 PA0/COM1
Figure 9.9 Port A Pin Configuration Port A has the following registers. * Port data register A (PDRA) * Port control register A (PCRA)
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Section 9 I/O Ports
9.9.1
Port Data Register A (PDRA)
PDRA is a register that stores data of port A.
Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 2 1 0 PA3 PA2 PA1 PA0 0 0 0 0 R/W R/W R/W R/W If port A is read while PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read.
9.9.2
Port Control Register A (PCRA)
PCRA selects inputs/outputs in bit units for pins to be used as general I/O ports of port A.
Bit 7 to 4 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 3 2 1 0 PCRA3 PCRA2 PCRA1 PCRA0 0 0 0 0 W W W W Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCRA is a write-only register. These bits are always read as 1.
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9.9.3
Pin Functions
The relationship between the register settings and the port functions is shown below. * PA3/COM4 pin
Register Name Bit Name Setting Value SGS3 to SGS0 B'0000 LPCR DTS1, DTS0 B'xx CMX x PCRA PCRA3 0 1 Other than B'0000 Other than B'11 0 0 1 Other than B'10 B'10 B'11 [Legend] x: Don't care x 1 x PA3 input pin PA3 output pin PA3 input pin PA3 output pin COM4 output pin Disabled COM4 output pin Pin Function
* PA2/COM3 pin
Register Name Bit Name Setting Value SGS3 to SGS0 B'0000 LPCR DTS1, CMX B'xx PCRA PCRA2 0 1 Other than B'0000 B'00 0 1 Other than B'00 [Legend] x: Don't care x PA2 input pin PA2 output pin PA2 input pin PA2 output pin COM3 output pin Pin Function
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* PA1/COM2 pin
Register Name Bit Name Setting Value SGS3 to SGS0 B'0000 LPCR DTS1, DTS0, CMX x PCRA PCRA1 0 1 Other than B'0000 B'000 0 1 Other than B'000 [Legend] x: Don't care x PA1 input pin PA1 output pin PA1 input pin PA1 output pin COM2 output pin Pin Function
* PA0/COM1 pin
Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'0000 PCRA PCRA0 0 1 Other than B'0000 [Legend] x: Don't care x PA0 input pin PA0 output pin COM1 output pin Pin Function
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9.10
Port B
Port B is an input-only port: its pins can also be configured to function as an interrupt input pin and analog input pin. Figure 9.10 shows the pin configuration.
PB7/AN7 PB6/AN6 PB5/AN5
Port B
PB4/AN4 PB3/AN3 PB2/AN2/IRQ3 PB1/AN1/IRQ1 PB0/AN0/IRQ0
Figure 9.10 Port B Pin Configuration Port B has the following registers. * Port data register B (PDRB) * Port mode register B (PMRB) 9.10.1 Port Data Register B (PDRB)
PDRB is a register that stores data of port B.
Bit 7 6 5 4 3 2 1 0 Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial Value R/W Description Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel by the CH3 to CH0 bits in AMR of the A/D converter, that pin is read as 0 regardless of the input voltage.
Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R
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Section 9 I/O Ports
9.10.2
Port Mode Register B (PMRB)
PMRB controls the selection of the port B pin functions.
Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4
ADTSTCHG 0
R/W
TEST/ADTRG Pin Function Switch Selects whether pin TEST/ADTRG is used as TEST or as ADTRG. 0: TEST pin 1: ADTRG input pin For details on the setting of the ADTRG input pin, refer to section 20.4.2, External Trigger Input Timing.
3 2
IRQ3
1 0
R/W
Reserved This bit is always read as 1 and cannot be modified. PB2/AN2/IRQ3* Pin Function Switch Selects whether pin PB2/AN2/IRQ3 is used as PB2/AN2 or as IRQ3. 0: PB2/AN2 input pin 1: IRQ3 input pin
1
IRQ1
0
R/W
PB1/AN1/IRQ1* Pin Function Switch Selects whether pin PB1/AN1/IRQ1 is used as PB1/AN1 or as IRQ1. 0: PB1/AN1 input pin 1: IRQ1 input pin
0
IRQ0
0
R/W
PB0/AN0/IRQ0* Pin Function Switch Selects whether pin PB0/AN0/IRQ0 is used as PB0/AN0 or as IRQ0. 0: PB0/AN0 input pin 1: IRQ0 input pin
Note:
*
For information on the power supply voltage (VCC) and analog power supply voltage (AVCC) when using this pin as an IRQn (n = 0, 1, 3) pin, see section 26.2.2 or 26.4.2, DC Characteristics.
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Section 9 I/O Ports
9.10.3
Pin Functions
The relationship between the register settings and the port functions is shown below. * PB7/AN7 pin
Register Name Bit Name Setting Value AMR CH3 to CH0 Other than B'1011 B'1011 PB7 input pin AN7 input pin Pin Function
* PB6/AN6 pin
Register Name Bit Name Setting Value AMR CH3 to CH0 Other than B'1010 B'1010 PB6 input pin AN6 input pin Pin Function
* PB5/AN5 pin
Register Name Bit Name Setting Value AMR CH3 to CH0 Other than B'1001 B'1001 PB5 input pin AN5 input pin Pin Function
* PB4/AN4 pin
Register Name Bit Name Setting Value AMR CH3 to CH0 Other than B'1000 B'1000 PB4 input pin AN4 input pin Pin Function
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Section 9 I/O Ports
* PB3/AN3 pin
Register Name Bit Name Setting Value AMR CH3 to CH0 Other than B'0111 B'0111 PB3 input pin AN3 input pin Pin Function
* PB2/AN2/IRQ3 pin
Register Name Bit Name Setting Value PMRB IRQ3 0 AMR CH3 to CH0 Other than B'0110 B'0110 1 Other than B'0110 B'0110 PB2 input pin AN2 input pin IRQ3 input pin Setting prohibited Pin Function
* PB1/AN1/IRQ1 pin
Register Name Bit Name Setting Value PMRB IRQ1 0 AMR CH3 to CH0 Other than B'0101 B'0101 1 Other than B'0101 B'0101 PB1 input pin AN1 input pin IRQ1 input pin Setting prohibited Pin Function
* PB0/AN0/IRQ0 pin
Register Name Bit Name Setting Value PMRB IRQ0 0 AMR CH3 to CH0 Other than B'0100 B'0100 1 Other than B'0100 B'0100 PB0 input pin AN0 input pin IRQ0 input pin Setting prohibited Pin Function
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Section 9 I/O Ports
9.11
Port C
Port C is an I/O port; its pins can also be configured to function as LCD segment output pins. Figure 9.11 shows the pin configuration.
PC7/SEG40 PC6/SEG39 PC5/SEG38
Port C
PC4/SEG37 PC3/SEG36 PC2/SEG35 PC1/SEG34 PC0/SEG33
Figure 9.11 Port C Pin Configuration Port C has the following registers. * Port data register C (PDRC) * Port control register C (PCRC) 9.11.1 Port Data Register C (PDRC)
PDRC is a register that stores data of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port C is read while PCRC bits are set to 1, the values stored in PDRC are read, regardless of the actual pin states. If port C is read while PCRC bits are cleared to 0, the pin states are read.
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Section 9 I/O Ports
9.11.2
Port Control Register C (PCRC)
PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C.
Bit 7 6 5 4 3 2 1 0 Bit Name PCRC7 PCRC6 PCRC5 PCRC4 PCRC3 PCRC2 PCRC1 PCRC0 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCRC bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. PCRC is a write-only register. These bits are always read as 1.
9.11.3
Pin Functions
The relationship between the register settings and the port functions is shown below. * PC7/SEG40 to PC0/SEG33 pins
(n = 7 to 0) Register Name Bit Name Setting Value LPCR SGS3 to SGS0 B'0xxx PCRC PCRCn 0 1 B'1xxx [Legend] x: Don't care x PCn input pin PCn output pin SEGn+33 output pin Pin Function
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Section 9 I/O Ports
9.12
Port E
Port E is an I/O port; its pins can also be configured to function as external interrupt input pins, SCI3_2 I/O pins, SCI3_3 I/O pins, and timer C input pin. Figure 9.12 shows its pin configuration.
PE7/TMIC(/IRQ0) PE6/UD PE5(/TXD32)
Port E
PE4(/RXD32) PE3(/SCK32/IRQ1) PE2/TXD33 PE1/RXD33 PE0/SCK33(/IRQ3)
Figure 9.12 Port E Pin Configuration Port E has the following registers. * Port data register E (PDRE) * Port control register E (PCRE) * Port mode register E (PMRE) 9.12.1 Port Data Register E (PDRE)
PDRE is a register that stores data of port E.
Bit 7 6 5 4 3 2 1 0 Bit Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If port E is read while PCRE bits are set to 1, the values stored in PDRE are read, regardless of the actual pin states. If port E is read while PCRE bits are cleared to 0, the pin states are read.
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Section 9 I/O Ports
9.12.2
Port Control Register E (PCRE)
PCRE selects inputs/outputs in bit units for pins of port E.
Bit 7 6 5 4 3 2 1 0 Bit Name PCRE7 PCRE6 PCRE5 PCRE4 PCRE3 PCRE2 PCRE1 PCRE0 Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PCRE bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCRE and in PDRE are valid when the corresponding pin is designated as a general I/O pin. PCRE is a write-only register. These bits are always read as 1.
9.12.3
Port Mode Register E (PMRE)
PMRE controls the selection of the port E pin functions.
Bit 7 to 5 4 Bit Name TMIC Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. PE7/TMIC Pin Function Switch 0: PE7 I/O pin 1: TMIC input pin 3 IRQ0 0 R/W PE7/IRQ0 Pin Function Switch 0: PE7 I/O pin 1: IRQ0 input pin 2 UD 0 R/W PE6/UD Pin Function Switch 0: PE6 I/O pin 1: UD input pin 1 IRQ1 0 R/W PE3/IRQ1 Pin Function Switch 0: PE3 I/O pin 1: IRQ1 input pin
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Section 9 I/O Ports
Bit 0
Bit Name IRQ3
Initial Value 0
R/W R/W
Description PE0/IRQ3 Pin Function Switch 0: PE0 I/O pin 1: IRQ3 input pin
9.12.4
Pin Functions
The relationship between the register settings and the port functions is shown below. * PE7/TMIC (/IRQ0) pin
Register Name Bit Name Setting Value PMRB IRQ0 0 IRQ0 1 PMRE TMIC x 0 PCRE PCRE7 x 0 1 1 [Legend] x: Don't care x IRQ0 input pin PE7 input pin PE7 output pin TMIC input pin Pin Function
Other than above
* PE6/UD pin
Register Name Bit Name Setting Value PMRE UD 0 PCRE PCRE6 0 1 1 [Legend] x: Don't care x PE6 input pin PE6 output pin UD input pin Pin Function
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Section 9 I/O Ports
* PE5 (/TXD32) pin
Register Name Bit Name Setting Value PFCR SC32S 0 SPCR SPC32 x PCRE PCRE5 0 1 1 0 0 1 1 [Legend] x: Don't care x PE5 input pin PE5 output pin PE5 input pin PE5 output pin TXD32 output pin Pin Function
* PE4 (/RXD32) pin
Register Name Bit Name Setting Value PFCR SC32S 0 SCR3_2 RE x PCRE PCRE4 0 1 1 0 0 1 1 [Legend] x: Don't care x PE4 input pin PE4 output pin PE4 input pin PE4 output pin RXD32 input pin Pin Function
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Section 9 I/O Ports
* PE3 (/SCK32/IRQ1) pin
Register Name Bit Name Setting Value PMRB IRQ1 0 PMRE IRQ1 1 PFCR SC32S x 0 SMR3_2 COM x x SCR3_2 CKE1 x x CKE0 x x PCRE PCRE3 x 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 x IRQ1 input pin PE3 input pin PE3 output pin PE3 input pin PE3 output pin SCK32 output pin SCK32 input pin Setting prohibited SCK32 output pin Setting prohibited SCK32 input pin Setting prohibited Pin Function
Other than above
[Legend] x: Don't care
* PE2/TXD33 pin
Register Name Bit Name Setting Value SPCR2 SPC33 0 PCRE PCRE2 0 1 1 [Legend] x: Don't care x PE2 input pin PE2 output pin TXD33 output pin Pin Function
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Section 9 I/O Ports
* PE1/RXD33 pin
Register Name Bit Name Setting Value SCR3_3 RE 0 PCRE PCRE1 0 1 1 [Legend] x: Don't care x PE1 input pin PE1 output pin RXD33 input pin Pin Function
* PE0/SCK33 (/IRQ3) pin
Register Name Bit Name Setting Value PMRB IRQ3 0 PMRE IRQ3 1 SMR3_3 COM x 0 SCR3_3 CKE1 x 0 CKE0 x 0 PCRE PCRE0 x 0 1 1 1 0 1 1 0 0 1 1 [Legend] x: Don't care 0 1 x IRQ3 input pin PE0 input pin PE0 output pin SCK33 output pin SCK33 input pin Setting prohibited SCK33 output pin Setting prohibited SCK33 input pin Setting prohibited Pin Function
Other than above
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Section 9 I/O Ports
9.13
Port F
Port F is an I/O port: its pins can also be configured to function as an external interrupt input pin, SCI3_1 I/O pins, and timer G input pin. Figure 9.13 shows the pin configuration.
PF3(/TXD31/IrTXD)
Port F
PF2(/RXD31/IrRXD) PF1(/SCK31/IRQ4) PF0/TMIG
Figure 9.13 Port F Pin Configuration Port F has the following registers. * Port data register F (PDRF) * Port control register F (PCRF) * Port mode register F (PMRF) 9.13.1 Port Data Register F (PDRF)
PDRF is a register that stores data of port F.
Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 3 2 1 0 PF3 PF2 PF1 PF0 0 0 0 0 R/W R/W R/W R/W Reserved The write value should always be 0. If port F is read while PCRF bits are set to 1, the values stored in PDRF are read, regardless of the actual pin states. If port F is read while PCRF bits are cleared to 0, the pin states are read.
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Section 9 I/O Ports
9.13.2
Port Control Register F (PCRF)
PCRF selects inputs/outputs in bit units for pins of port F.
Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 3 2 1 0 PCRF3 PCRF2 PCRF1 PCRF0 0 0 0 0 W W W W Reserved The write value should always be 0. Setting a PCRF bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCRF and in PDRF are valid when the corresponding pin is designated as a general I/O pin. PCRF is a write-only register. These bits are always read as 1.
9.13.3
Port Mode Register F (PMRF)
PMRF controls the selection of the pin functions on port F.
Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 IRQ4 0 R/W PF1/IRQ4 Pin Function Switch 0: PF1 I/O pin 1: IRQ4 input pin 1 NCS 0 R/W Controls usage of the TMIG noise cancellation circuit. 0: Noise cancellation is disabled 1: Noise cancellation is enabled 0 TMIG 0 R/W PF0/TMIG Pin Function Switch 0: PF0 I/O pin 1: TMIG input pin
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Section 9 I/O Ports
9.13.4
Pin Functions
The relationship between the register settings and the port functions is shown below. * PF3 (/TXD31/IrTXD) pin
Register Name Bit Name Setting Value PFCR SC31S 0 SPCR SPC31 x IrCR IrE x PCRF PCRF3 0 1 1 0 0 1 1 [Legend] x: Don't care 0 1 x PF3 input pin PF3 output pin PF3 input pin PF3 output pin TXD31 output pin IrTXD output pin Pin Function
* PF2 (/RXD31/IrRXD) pin
Register Name Bit Name Setting Value PFCR SC31S 0 SCR3_1 RE x IrCR IrE x PCRF PCRF2 0 1 1 0 0 1 1 [Legend] x: Don't care 0 1 x PF2 input pin PF2 output pin PF2 input pin PF2 output pin RXD31 input pin IrRXD input pin Pin Function
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Section 9 I/O Ports
* PF1 (/SCK31/IRQ4) pin
Register Name Bit Name Setting Value PMR9 IRQ4 0 PMRF IRQ4 1 PFCR SC31S x 0 SMR3_1 COM x x SCR3_1 CKE1 x x CKE0 x x PCRF PCRF1 x 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 x IRQ4 input pin PF1 input pin PF1 output pin PF1 input pin PF1 output pin SCK31 output pin SCK31 input pin Setting prohibited SCK31 output pin Setting prohibited SCK31 input pin Setting prohibited Pin Function
Other than above
[Legend] x: Don't care
* PF0/TMIG pin
Register Name Bit Name Setting Value PMRF TMIG 0 PCRF PCRF0 0 1 1 [Legend] x: Don't care x PF0 input pin PF0 output pin TMIG input pin Pin Function
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Section 9 I/O Ports
9.14
9.14.1
Input/Output Data Inversion
Serial Port Control Register, Serial Port Control Register 2 (SPCR, SPCR2)
SPCR switches input/output data inversion of the RXD (IrRXD) and TXD (IrTXD) pins. Figure 9.14 shows a input/output data inversion function.
SCINV0 SCINV2 SCINV4 PE1/RXD33 P31/RXD32 (PE4/RXD32) P41/RXD31/IrRXD (PF2/RXD31/IrRXD) RXD33 RXD32 RXD31/IrRXD SCINV1 SCINV3 SCINV5 TXD33 TXD32 TXD31/IrTXD
PE2/TXD33 P32/TXD32 (PE5/TXD32) P42/TXD31/IrTXD (PF3/TXD31/IrTXD)
Figure 9.14 Input/Output Data Inversion Function * SPCR
Bit 7 6 5 Bit Name SPC32 Initial Value 1 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. P32/TXD32/SCL (PE5/TXD32) Pin Function Switch Selects whether pin P32/TXD32/SCL (PE5/TXD32) is used as P32/SCL (PE5) or as TXD32. 0: P32/ SCL (PE5) I/O pin 1: TXD32 output pin* Note: Set the TE bit in SCR3_2 after having set this bit to 1.
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Section 9 I/O Ports
Bit 4
Bit Name SPC31
Initial Value 0
R/W R/W
Description P42/TXD31/IrTXD/TMOFH (PF3/TXD31/IrTXD) Pin Function Switch Selects whether pin P42/TXD31/IrTXD/TMOFH (PF3/TXD31/IrTXD) is used as P42/TMOFH (PF3) or as TXD31/IrTXD. 0: P42 (PF3) I/O pin or TMOFH output pin 1: TXD31/IrTXD output pin* Note: Set the TE bit in SCR3_1 after having set this bit to 1.
3
SCINV3
0
R/W
TXD32 Pin Output Data Inversion Switch Specifies whether the logic level of output data of the TXD32 pin is to be inverted or not. 0: TXD32 output data is not inverted 1: TXD32 output data is inverted
2
SCINV2
0
R/W
RXD32 Pin Input Data Inversion Switch Specifies whether the logic level of input data of the RXD32 pin is to be inverted or not. 0: RXD32 input data is not inverted 1: RXD32 input data is inverted
1
SCINV1
0
R/W
TXD31/IrTXD Pin Output Data Inversion Switch Specifies whether the logic level of output data of the TXD31/IrTXD pin is to be inverted or not. 0: TXD31/IrTXD output data is not inverted 1: TXD31/IrTXD output data is inverted
0
SCINV0
0
R/W
RXD31/IrRXD Pin Input Data Inversion Switch Specifies whether the logic level of input data of the RXD31/IrRXD pin is to be inverted or not. 0: RXD31/IrRXD input data is not inverted 1: RXD31/IrRXD input data is inverted
Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated.
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Section 9 I/O Ports
* SPCR2
Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 SPC33 0 R/W PE2/TXD33 Pin Function Switch Selects whether pin PE2/TXD33 is used as PE2 or as TXD33. 0: PE2 I/O pin 1: TXD33 output pin Set the TE bit in SCR3_3 after having set this bit to 1. 3 2 1 SCINV5 1 1 0 R/W Reserved These bits are always read as 1 and cannot be modified. TXD33 Pin Output Data Inversion Switch Specifies whether the logic level of output data of the TXD33 pin is inverted. 0: TXD33 output data is not inverted 1: TXD33 output data is inverted 0 SCINV4 0 R/W RXD33 Pin Input Data Inversion Switch Specifies whether the logic level of input data of the RXD33 pin is inverted. 0: RXD33 input data is not inverted 1: RXD33 input data is inverted Note: When the serial port control register 2 is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register 2, modification must be made in a state in which data changes are invalidated.
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Section 9 I/O Ports
9.15
9.15.1
Port Function Switch
Port Function Control Register (PFCR)
PFCR controls the assignments of pins for SCI3_1 and SCI3_2 and the functions of other pins.
Bit 7 6 Bit Name Initial Value R/W R/W R/W Description TMOW/CLKOUT Pin Function Switch 00: CLKOUT output pin (OSC) 01: CLKOUT output pin (OSC/2) 10: CLKOUT output pin (OSC/4) 11: TMOW output pin 5 4 PWM4 1 0 R/W Reserved This bit is always read as 1 and cannot be modified. P93/PWM4 Pin Function Switch 0: P93 I/O pin 1: PWM4 output pin 3 PWM3 0 R/W P92/PWM3 Pin Function Switch 0: P92 I/O pin 1: PWM3 output pin 2 1 SC32S 1 0 R/W Reserved This bit is always read as 1 and cannot be modified. SCI3_2 Pin Assignment Select 0: TXD32 is assigned to P32 RXD32 is assigned to P31 SCK32 is assigned to P30 1: TXD32 is assigned to PE5 RXD32 is assigned to PE4 SCK32 is assigned to PE3
CLKOUT1 1 CLKOUT0 1
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Section 9 I/O Ports
Bit 0
Bit Name SC31S
Initial Value 0
R/W R/W
Description SCI3_1 Pin Assignment Select 0: TXD31 is assigned to P42 RXD31 is assigned to P41 SCK31 is assigned to P40 1: TXD31 is assigned to PF3 RXD31 is assigned to PF2 SCK31 is assigned to PF1
9.16
9.16.1
Usage Notes
How to Handle Unused Pin
If an I/O pin not used by the user system is floating, pull it up or down. * If an unused pin is an input pin, it is recommended to handle it in one of the following ways: Pull it up to Vcc with an on-chip pull-up MOS. Pull it up to Vcc with an external resistor of approximately 100 k. Pull it down to Vss with an external resistor of approximately 100 k. For a pin also used by the A/D converter, pull it up to AVcc. With an external resistor of approximately 100 k. * If an unused pin is an output pin, it is recommended to handle it in one of the following ways: Set the output of the unused pin to high and pull it up to Vcc with an external resistor of approximately 100 k. Set the output of the unused pin to low and pull it down to GND with an external resistor of approximately 100 k. 9.16.2 Input Characteristics Difference due to Pin Function
When the functions of pins IRQ0, IRQ1, IRQ3, IRQ4, IRQACE, WKP0 to WKP7, AEVL, AEVH, TMIC, TMIF, TMIG, SCK31 to SCK33, SDA, and SCL are selected, the corresponding pins have the schmitt-trigger input characteristics, which are different from the ones when they are used as the port input pins. For example, the input high voltage and the input low voltage of the PB0/AN0/IRQ0 pin differ when the pin is used as PB0 input or IRQ0 input. For details, refer to tables 26.2 and 26.12.
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Section 10 Realtime Clock (RTC)
Section 10 Realtime Clock (RTC)
The realtime clock (RTC) is a timer used to count periods of time ranging from a second to a week. Interrupts can be generated at intervals ranging from 0.25 seconds to a week. Figure 10.1 is a block diagram of the RTC.
10.1
Features
* Counts seconds, minutes, hours, and day-of-week * Start/stop function * Reset function * Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes * Periodic (0.25 seconds, 0.5 seconds, one second, minute, hour, day, and week) interrupts * 8-bit free running counter * Selection of clock source * Module standby mode allows this module to enter standby mode independently when it is not in use (for details, see section 6.4, Module Standby Function).
PSS 32-kHz oscillator circuit RTCCSR 1/4 RSECDR RMINDR RHRDR TMOW Clock count control circuit RWKDR RTCCR1 RTCCR2 RTCFLG Interrupt control circuit RWKDR: RTCCR1: RTCCR2: RTCFLG: PSS: Day-of-week date register RTC control register 1 RTC control register 2 RTC interrupt flag register Prescaler S
[Legend] RTCCSR: Clock source select register RSECDR: Second date register/ free running counter data register RMINDR: Minute date register RHRDR: Hour date register
Figure 10.1 Block Diagram of RTC
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Internal data bus
Interrupt
Section 10 Realtime Clock (RTC)
10.2
Input/Output Pin
Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration
Pin Name Clock output Abbreviation TMOW I/O Output Function RTC divided clock output
10.3
Register Descriptions
The RTC has the following registers. * Second data register/free running counter data register (RSECDR) * Minute data register (RMINDR) * Hour data register (RHRDR) * Day-of-week data register (RWKDR) * RTC control register 1 (RTCCR1) * RTC control register 2 (RTCCR2) * Clock source select register (RTCCSR) * RTC Interrupt flag register (RTCFLG)
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Section 10 Realtime Clock (RTC)
10.3.1
Second Data Register/Free Running Counter Data Register (RSECDR)
RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit read register used as a counter, when it operates as a free running counter. For more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, Data Reading Procedure.
Bit 7 Bit Name BSY Initial Value --/(0)* R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 Note: * SC12 SC11 SC10 SC03 SC02 SC01 SC00 --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* R/W R/W R/W R/W R/W R/W R/W Counting One's Position of Seconds Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. Counting Ten's Position of Seconds Counts on 0 to 5 for 60-second counting.
This is the initial value after a reset by the RST bit in RTCCR1.
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Section 10 Realtime Clock (RTC)
10.3.2
Minute Data Register (RMINDR)
RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59.
Bit 7 Bit Name BSY Initial Value --/(0)* R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 Note: * MN12 MN11 MN10 MN03 MN02 MN01 MN00 --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* R/W R/W R/W R/W R/W R/W R/W Counting One's Position of Minutes Counts on 0 to 9 once per minute. When a carry is generated, 1 is added to the ten's position. Counting Ten's Position of Minutes Counts on 0 to 5 for 60-minute counting.
This is the initial value after a reset by the RST bit in RTCCR1.
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Section 10 Realtime Clock (RTC)
10.3.3
Hour Data Register (RHRDR)
RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1.
Bit 7 Bit Name BSY Initial Value --/(0)* R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 Note: * -- HR11 HR10 HR03 HR02 HR01 HR00 0 --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* -- R/W R/W R/W R/W R/W R/W Reserved This bit is always read as 0. Counting Ten's Position of Hours Counts on 0 to 2 for ten's position of hours. Counting One's Position of Hours Counts on 0 to 9 once per hour. When a carry is generated, 1 is added to the ten's position.
This is the initial value after a reset by the RST bit in RTCCR1.
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Section 10 Realtime Clock (RTC)
10.3.4
Day-of-Week Data Register (RWKDR)
RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0.
Bit 7 Bit Name BSY Initial Value --/(0)* R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 to 3 2 1 0 -- WK2 WK1 WK0 All 0 --/(0)* --/(0)* --/(0)* -- R/W R/W R/W Reserved These bits are always read as 0. Day-of-Week Counting Day-of-week is indicated with a binary code 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Setting prohibited Note: * This is the initial value after a reset by the RST bit in RTCCR1.
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Section 10 Realtime Clock (RTC)
10.3.5
RTC Control Register 1 (RTCCR1)
RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2.
Bit 7 Bit Name RUN Initial Value --/(0)* R/W R/W Description RTC Operation Start 0: Stops RTC operation 1: Starts RTC operation 6 12/24 --/(0)* R/W Operating Mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode. RHRDR counts on 0 to 23. 5 PM --/(0)* R/W A.m./P.m. 0: Indicates a.m. when RTC is in the 12-hour mode. 1: Indicates p.m. when RTC is in the 12-hour mode. 4 RST 0 R/W Reset 0: Normal operation 1: Resets registers and control circuits except RTCCSR and this bit. Clear this bit to 0 after having been set to 1. 3 2 to 0 Note: * -- -- -- All 0 R/W -- Reserved The write value should be 0. Reserved These bits are always read as 0. This is the initial value after a reset by the RST bit in RTCCR1.
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Section 10 Realtime Clock (RTC)
Noon 24-hour count 0 12-hour count 0 PM 1 1 2 2 3 3 4 4 567 567 0 (Morning) 8 8 9 10 11 12 13 14 15 16 17 9 10 11 0 1 2 3 4 5 1 (Afternoon)
24-hour count 18 19 20 21 22 23 0 12-hour count 6 7 8 9 10 11 0 1 (Afternoon) 0 PM
Figure 10.2 Definition of Time Expression
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Section 10 Realtime Clock (RTC)
10.3.6
RTC Control Register 2 (RTCCR2)
RTCCR2 controls RTC periodic interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds. Enabling interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds sets the corresponding flag to 1 in the RTC interrupt flag register (RTCFLG) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter.
Bit 7 Bit Name FOIE Initial Value --/(0)* R/W R/W Description Free Running Counter Overflow Interrupt Enable 0: Disables an overflow interrupt 1: Enables an overflow interrupt 6 WKIE --/(0)* R/W Week Periodic Interrupt Enable 0: Disables a week periodic interrupt 1: Enables a week periodic interrupt 5 DYIE --/(0)* R/W Day Periodic Interrupt Enable 0: Disables a day periodic interrupt 1: Enables a day periodic interrupt 4 HRIE --/(0)* R/W Hour Periodic Interrupt Enable 0: Disables an hour periodic interrupt 1: Enables an hour periodic interrupt 3 MNIE --/(0)* R/W Minute Periodic Interrupt Enable 0: Disables a minute periodic interrupt 1: Enables a minute periodic interrupt 2 1SEIE --/(0)* R/W One-Second Periodic Interrupt Enable 0: Disables a one-second periodic interrupt 1: Enables a one-second periodic interrupt 1 05SEIE --/(0)* R/W 0.5-Second Periodic Interrupt Enable 0: Disables a 0.5-second periodic interrupt 1: Enables a 0.5-second periodic interrupt 0 025SEIE --/(0)* R/W 0.25-Second Periodic Interrupt Enable 0: Disables a 0.25-second periodic interrupt 1: Enables a 0.25-second periodic interrupt Note: * This is the initial value after a reset by the RST bit in RTCCR1.
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Section 10 Realtime Clock (RTC)
10.3.7
Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than w/4 is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to the FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode. The w clock is output in active, sleep, subactive, subsleep, and watch modes.
Bit 7 6 5 4 Bit Name -- RCS6 RCS5 SUB32K Initial Value --/(0)* 0 0 0 R/W R R/W R/W R/W Description Reserved This bit cannot be modified. Clock Output Selection Select a clock output from the TMOW pin when setting the TMOW bit in PMR3 to 1. 000: /4 010: /8 100: /16 110: /32 xx1: w 3 2 1 0 RCS3 RCS2 RCS1 RCS0 1 0 0 0 R/W R/W R/W R/W Clock Source Selection 0000: /8 Free running counter operation 0001: /32 Free running counter operation 0010: /128 Free running counter operation 0011: /256 Free running counter operation 0100: /512 Free running counter operation 0101: /2048 Free running counter operation 0110: /4096 Free running counter operation 0111: /8192 Free running counter operation 1000 : w/4 RTC operation 1001 to 1111: Setting prohibited [Legend] x: Don't care. Note: * This is the initial value after a reset by the RST bit in RTCCR1.
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Section 10 Realtime Clock (RTC)
10.3.8
RTC Interrupt Flag Register (RTCFLG)
RTCFLG sets the corresponding flag when an interrupt occurs. Each flag is not cleared automatically even if the interrupt is accepted. To clear the flag, 0 should be written to the flag.
Bit 7 Bit Name FOIFG Initial Value /(0)*
2
R/W 1 R/W*
6
WKIFG
/(0)*
2
R/W*
1
5
DYIFG
/(0)*
2
R/W*
1
4
HRIFG
/(0)*
2
R/W*
1
3
MNIFG
/(0)*
2
R/W*
1
2
SEIFG
/(0)*
2
R/W*
1
1
05SEIFG
/(0)*
2
R/W*
1
0
025SEIFG /(0)*
2
R/W*
1
Description [Setting condition] A free running counter overflows [Clearing condition] 0 is written to FOIFG when FOIFG = 1 [Setting condition] A week periodic interrupt occurs [Clearing condition] 0 is written to WKIFG when WKIFG = 1 [Setting condition] A day periodic interrupt occurs [Clearing condition] 0 is written to DYIFG when DYIFG = 1 [Setting condition] An hour periodic interrupt occurs [Clearing condition] 0 is written to HRIFG when HRIFG = 1 [Setting condition] A minute periodic interrupt occurs [Clearing condition] 0 is written to MNIFG when MNIFG = 1 [Setting condition] A one-second periodic interrupt occurs [Clearing condition] 0 is written to SEIFG when SEIFG = 1 [Setting condition] A 0.5-second periodic interrupt occurs [Clearing condition] 0 is written to 05SEIFG when 05SEIFG = 1 [Setting condition] A 0.25-second periodic interrupt occurs [Clearing condition] 0 is written to 025SEIFG when 025SEIFG = 1
Notes: 1. Only 0 can be written here, to clear the flag. 2. This is the initial value after a reset by the RST bit in RTCCR1.
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Section 10 Realtime Clock (RTC)
10.4
10.4.1
Operation
Initial Settings of Registers after Power-On
The RTC registers that store second, minute, hour, and day-of-week data, control registers, and interrupt registers are not initialized by a RES input, or by a reset source caused by a watchdog timer. Therefore, all registers must be set to their initial values after power-on. Once the register settings are made, the RTC provides an accurate time as long as power is supplied regardless of a RES input. 10.4.2 Initial Setting Procedure
Figure 10.3 shows the procedure for the initial setting of the RTC. To set the RTC again, also follow this procedure.
RUN in RTCCR1 = 0 RST in RTCCR1 = 1 RST in RTCCR1 = 0 Set RTCCSR, RSECDR, RMINDR, RHRDR, RWKDR, 12/24 in RTCCR1, and PM RUN in RTCCR1 = 1
RTC operation is stopped.
RTC registers and clock count controller are reset.
Clock output and clock source are selected and second, minute, hour, day-of-week, operating mode, and a.m/p.m are set. RTC operation is started.
Figure 10.3 Initial Setting Procedure
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Section 10 Realtime Clock (RTC)
10.4.3
Data Reading Procedure
When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY bit is set to 1, the registers are updated, and the BSY bit is cleared to 0. 2. Making use of interrupts, read from the second, minute, hour, and day-of week registers after the corresponding flag of RTCFLG is set to 1 and the BSY bit is confirmed to be 0. 3. Read from the second, minute, hour, and day-of week registers twice in a row, and if there is no change in the read data, the read data is used.
Before update BSY bit = 0 RWKDR = H'03, RHDDR = H'13, RMINDR = H'46, RSECDR = H'59
Processing flow
(1) Day-of-week data register read (2) Hour data register read (3) Minute data register read
H'03 H'13 H'46
BSY bit -> 1 (under data update) After update BSY bit -> 0 RWKDR = H'03, RHDDR = H'13, RMINDR = H'47, RSECDR = H'00
(4) Second data register read
H'00
Figure 10.4 Example: Reading of Inaccurate Time Data
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Section 10 Realtime Clock (RTC)
10.5
Interrupt Sources
There are eight kinds of RTC interrupts: a free-running counter overflow, week interrupt, day interrupt, hour interrupt, minute interrupt, one-second interrupt, 0.5-second interrupt, and 0.25second interrupt. When using an interrupt, set the IENRTC (RTC interrupt request enable) bit in IENR1 to 1 last after other registers are set. When an interrupt request of the RTC occurs, the corresponding flag in RTCFLG is set to 1. When clearing the flag, write 0. Table 10.2 shows a interrupt sources. Table 10.2 Interrupt Sources
Interrupt Name Overflow interrupt Week periodic interrupt Day periodic interrupt Hour periodic interrupt Minute periodic interrupt One-second periodic interrupt 0.5-second periodic interrupt 0.25-second periodic interrupt Interrupt Source Occurs when the free running counter is overflowed. Interrupt Enable Bit FOIE
Occurs every week when the day-of-week date WKIE register value becomes 0. Occurs every day when the day-of-week date register is counted. DYIE
Occurs every hour when the hour date register HRIE is counted. Occurs every minute when the minute date register is counted. Occurs every second when the one-second date register is counted. Occurs every 0.5 seconds. Occurs every 0.25 seconds. MNIE 1SEIE 05SEIE 025SEIE
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Section 10 Realtime Clock (RTC)
10.6
10.6.1
Usage Notes
Note on Clock Count
The subclock must be connected to the 32.768-kHz resonator. When the 38.4-kHz resonator etc. is connected, the correct time count is not possible. 10.6.2 Note when Using RTC Interrupts
The RTC registers are not reset by a RES input, power-on, or overflow of the watchdog timer, and their values are undefined after power-on. When using RTC interrupts, make sure to initialize the values before setting the IENRTC bit in IENR1 to 1.
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Section 10 Realtime Clock (RTC)
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Section 11 Timer C
Section 11 Timer C
Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload.
11.1
Features
Features of timer C are given below. * Choice of nine internal clock sources (/8192, /2048, /512, /64, /16, /4, W/4, W/256, and W/1024) or an external clock (can be used to count external events). * An interrupt is requested when the counter overflows. * Up/down-counter switching is selected either by the register specification or the external input level specification. * Subactive mode or subsleep mode operation is possible when W/4, W/256, or W/1024 is selected as the internal clock, or when an external clock is selected. * Use of module standby mode enables this module to be placed in standby mode independently when not used (for details, see section 6.4, Module Standby Function).
TMC
UD
TMIC w/4
PSS
TCC
TLC PSW IRRTC
[Legend] TMC: Timer mode register C TCC: Timer counter C TLC: Timer load register C IRRTC: Timer C overflow interrupt request flag PSS: Prescaler S PSW: Prescaler W
Figure 11.1 Block Diagram of Timer C
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Internal data bus
Section 11 Timer C
11.2
Input/Output Pins
Table 11.1 shows the input/output pins of the timer C. Table 11.1 Pin Configuration
Name Timer C event input Timer C up/down select Abbreviation I/O TMIC UD Input Input Function Input pin for event input to TCC Timer C up/down-count selection
11.3
Register Descriptions
Timer C has the following registers. For details on clock halt register 3 (CKSTPR3), see section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3). * Timer mode register C (TMC) * Timer counter C (TCC) * Timer load register (TLC) * Clock halt register 3 (CKSTPR3)
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Section 11 Timer C
11.3.1
Timer Mode Register C (TMC)
TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and performing up/down-counter control. Upon reset, TMC is initialized to H'10.
Bit 7 Bit Name TMC7 Initial Value 0 R/W R/W Description Auto-Reload Function Select Selects whether timer C is used as an interval timer or auto-reload timer. 0: Interval timer function 1: Auto-reload function 6 5 TMC6 TMC5 0 0 R/W R/W Counter Up/Down Control Specifies whether TCC functions as an up-counter or down-counter, or whether selection of counting up or down is controlled by the input signal level on the UD pin. 00: TCC is an up-counter 01: TCC is a down-counter 1x: Selection through the signal level on the UD pin UD pin input high: Down-counter UD pin input low: Up-counter 4
--
1
--
Reserved This bit is always read as 1 and cannot be modified.
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Section 11 Timer C
Bit 3 2 1 0
Bit Name TMC3 TMC2 TMC1 TMC0
Initial Value 0 0 0 0
R/W R/W
Description Clock Select TMC3 to TMC0 select the clock input for TCC. For the counting of external events, either the rising or falling edge can be selected. x000: Internal clock counting on /8192 x001: Internal clock counting on /2048 x010: Internal clock counting on /512 x011: Internal clock counting on /64 x100: Internal clock counting on /16 0101: Internal clock counting on /4 0110: Internal clock counting on W/1024 1101: Internal clock counting on W/256 1110: Internal clock counting on W/4 0111: Counting falling edges of external events (TMIC)* 1111: Counting rising edges of external events (TMIC)*
[Legend] x: Don't care Note: * The TMIC bit in the port mode register E (PMRE) must be set to 1 before the TMC3 to TMC0 bits are set to B'x111.
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Section 11 Timer C
11.3.2
Timer Counter C (TCC)
TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC3 to TMC0 in the timer mode register C (TMC). TCC values can be read by the CPU at any time. When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1. TCC is allocated to the same address as TLC. Upon reset, TCC is initialized to H'00. 11.3.3 Timer Load Register C (TLC)
TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC). When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC starts counting up/down from that value. When TCC overflows or underflows during operation in auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow period can be set within the range of 1 to 256 input clocks. The same address is allocated to TLC as to TCC. Upon reset, TLC is initialized to H'00. 11.3.4 Clock Halt Register 3 (CKSTPR3)
For details on placing timer C in and taking it out of standby mode (this is controlled by the TCCKSTP bit in CKSTPR3) see section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3).
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Section 11 Timer C
11.4
11.4.1
Timer Operation
Interval Timer Operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit interval timer. Upon reset, TCC is initialized to H'00 and TMC to H'10, so TCC continues up-counting as an interval up-counter without halting immediately after a reset. The timer C operating clock is selected from nine internal clock signals output by prescalers S and W, or an external clock input at pin TMIC. The selection is made by bits TMC3 to TMC0 in TMC. TCC up/down-count control can be specified by bits TMC6 and TMC5 in TMC, or selected by the input signal level on the UD pin. After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow (underflow), setting bit IRRTC in IRR2 to 1. If IENTC = 1 in interrupt enable register 2 (IENR2), a CPU interrupt is requested. At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again. During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: For details on interrupts, see section 4, Interrupt Controller.
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Section 11 Timer C
11.4.2
Auto-Reload Timer Operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that value. The overflow/underflow period can be set within a range from 1 to 256 input clocks, depending on the TLC value. The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in TCC. 11.4.3 Event Counter Operation
Timer C can operate as an event counter, with the TMIC pin as the event input pin. External event counting is selected by setting bits TMC3 to TMC0 in the timer mode register C (TMC) to B'0111 or B'1111, and setting the TMIC bit in PMRE to 1. TCC counts up/down at the rising/falling edge of an external event signal input at the TMIC pin. The external event input signal is not counted correctly if it does not satisfy the high width or low width of the input pin. 11.4.4 TCC Up/Down Control by the External Input Pin
With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 in TMC is set to 1, TCC functions as an up-counter when UD pin input is low, and as a down-counter when high. When using UD pin input, set the UD bit in PMRE to 1.
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Section 11 Timer C
11.5
Timer C Operation States
Table 11.2 summarizes the timer C operation states. Table 11.2 Timer C Operation States
Module Operation Mode TCC Interval Reset Reset Active Functioning*
1
Sleep Functioning*
1
Watch Functioning/ Halted*
2
Sub-active Functioning/ Halted*
3
Sub-sleep Functioning/ Halted*
3
Standby Halted
Standby Halted
Auto reload
Reset
Functioning*
1
Functioning*
1
Functioning/ Halted*
2
Functioning/ Halted*
3
Functioning/ Halted*
3
Halted
Halted
TMC
Reset
Functioning
Retained
Retained
Functioning
Retained
Retained
Retained
Notes: 1. When W/4, W/256, or W/1024 is selected as the TCC internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/ (s). 2. When the counter is operated in watch mode, select W/4, W/256, or W/1024 as the clock. 3. When the counter is operated in subactive mode or subsleep mode, either select W/4, W/256, or W/1024 as the internal clock or select an external clock. The counter will not operate on any other internal clock. If W /4 is selected as the internal clock for the counter when W/8 has been selected as subclock SUB, the lower 2 bits of the counter operate on the same cycle, and the operation of the least significant bit is unrelated to the operation of the counter.
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Section 12 Timer F
Section 12 Timer F
The timer F is a 16-bit timer having an output compare function. The timer F also provides for external event counting, and counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Thus, it can be applied to various systems. The timer F can also be used as two independent 8-bit timers (timer FH and timer FL). Figure 12.1 shows a block diagram of the timer F.
12.1
Features
* Choice of five counter input clocks Internal clocks (/32, /16, /4, and W/4) or external clocks can be selected. * Toggle output function Toggle output is performed to the TMOFH or TMOFL pin using a compare match signal. The initial value of toggle output can be set. * Counter resetting by a compare match signal * Two interrupt sources: One compare match, one overflow * Choice of 16-bit or 8-bit mode by settings of bits CKSH2 to CKSH0 in TCRF * Can operate in watch mode, subactive mode, and subsleep mode When W/4 is selected as an internal clock, the timer F can operate in watch mode, subactive mode, and subsleep mode. * Module standby mode enables this module to be placed in standby mode independently when it is not in use (for details, refer to section 6.4, Module Standby Function).
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Section 12 Timer F
PSS
IRRTFL
TCRF
W/4 TMIF TMOFL Toggle circuit
TCFL
Comparator
OCRFL
TCFH Toggle circuit
TMOFH
Comparator
Match
[Legend] TCRF: TCSRF: TCFH: TCFL: OCRFH: OCRFL: IRRTFH: IRRTFL: PSS: Timer control register F Timer control status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S
OCRFH
TCSRF IRRTFH
Figure 12.1 Block Diagram of Timer F
12.2
Input/Output Pins
Table 12.1 shows the input/output pins of the timer F. Table 12.1 Pin Configuration
Pin Name Timer F event input Timer FH output Timer FL output Abbreviation TMIF TMOFH TMOFL I/O Input Output Output Function Event input pin to TCFL Timer FH toggle output pin Timer FL toggle output pin
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Internal data bus
Section 12 Timer F
12.3
Register Descriptions
The timer F has the following registers. * Timer counters FH and FL (TCFH, TCFL) * Output compare registers FH and FL (OCRFH, OCRFL) * Timer control register F (TCRF) * Timer control/status register F (TCSRF) 12.3.1 Timer Counters FH and FL (TCFH, TCFL)
TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters. TCFH and TCFL are initialized to H'00 upon a reset. (1) 16-Bit Mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock is selected by bits CKSL2 to CKSL0 in TCRF. TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an interrupt request is sent to the CPU. (2) 8-Bit Mode (TCFH/TCFL)
When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to CKSL0) in TCRF. TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
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Section 12 Timer F
12.3.2
Output Compare Registers FH and FL (OCRFH, OCRFL)
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers. (1) 16-Bit Mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin by means of compare matches, and the output level can be set by means of the TOLH bit in TCRF. (2) 8-Bit Mode (OCRFH/OCRFL)
When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL. When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in IENR2 is 1 at this time, an interrupt request is sent to the CPU. Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare matches, and the output level can be set by means of the TOLH (TOLL) bit in TCRF.
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Section 12 Timer F
12.3.3
Timer Control Register F (TCRF)
TCRF switches between 16-bit mode and 8-bit mode, selects the input clock from among four counter input clock sources, and selects the output level of the TMOFH and TMOFL pins.
Bit 7 Bit Name TOLH Initial Value 0 R/W W Description Toggle Output Level H Sets the TMOFH pin output level. 0: Low level 1: High level Clock Select H Select the clock input to TCFH from among four internal clock sources or TCFL overflow. 000: 16-bit mode, counting on TCFL overflow signal 001: 16-bit mode, counting on TCFL overflow signal 010: 16-bit mode, counting on TCFL overflow signal 011: Using prohibited 100: 8-bit mode, counting on /32 101: 8-bit mode, counting on /16 110: 8-bit mode, counting on /4 111: 8-bit mode, counting on W/4 3 TOLL 0 W Toggle Output Level L Sets the TMOFL pin output level. 0: Low level 1: High level
6 5 4
CKSH2 CKSH1 CKSH0
0 0 0
W W W
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Section 12 Timer F
Bit 2 1 0
Bit Name CKSL2 CKSL1 CKSL0
Initial Value 0 0 0
R/W W W W
Description Clock Select L Select the clock input to TCFL from among four internal clock sources or external event input. 000: Counting on a rising or falling edge of an external event (on the TMIF pin)* 001: Counting on a rising or falling edge of an external event (on the TMIF pin)* 010: Counting on a rising or falling edge of an external event (on the TMIF pin)* 011: Using prohibited 100: Internal clock: counting on /32 101: Internal clock: counting on /16 110: Internal clock: counting on /4 111: Internal clock: counting on W/4
Note:
*
The TMIFEG bit in IEGR selects which edge of an external event is used for counting.
12.3.4
Timer Control/Status Register F (TCSRF)
TCSRF performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Bit 7 Bit Name OVFH Initial Value 0 R/W Description [Setting condition] TCFH overflows from H'FF to H'00 [Clearing condition] Writing of 0 to bit OVFH after reading OVFH = 1 6 CMFH 0 R/(W)* Compare Match Flag H This is a status flag indicating that TCFH has matched OCRFH. [Setting condition] The TCFH value matches the OCRFH value [Clearing condition] Writing of 0 to bit CMFH after reading CMFH = 1
R/(W)* Timer Overflow Flag H
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Section 12 Timer F
Bit 5
Bit Name OVIEH
Initial Value 0
R/W R/W
Description Timer Overflow Interrupt Enable H Selects enabling or disabling of interrupt generation when TCFH overflows. 0: TCFH overflow interrupt request is disabled 1: TCFH overflow interrupt request is enabled
4
CCLRH
0
R/W
Counter Clear H In 16-bit mode, this bit selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, this bit selects whether TCFH is cleared when TCFH and OCRFH match. In 16-bit mode: 0: TCF clearing by compare match is disabled 1: TCF clearing by compare match is enabled In 8-bit mode: 0: TCFH clearing by compare match is disabled 1: TCFH clearing by compare match is enabled
3
OVFL
0
R/(W)* Timer Overflow Flag L This is a status flag indicating that TCFL has overflowed. [Setting condition] TCFL overflows from H'FF to H'00 [Clearing condition] Writing of 0 to bit OVFL after reading OVFL = 1
2
CMFL
0
R/(W)* Compare Match Flag L This is a status flag indicating that TCFL has matched OCRFL. [Setting condition] The TCFL value matches the OCRFL value [Clearing condition] Writing of 0 to bit CMFL after reading CMFL = 1
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Section 12 Timer F
Bit 1
Bit Name OVIEL
Initial Value 0
R/W R/W
Description Timer Overflow Interrupt Enable L Selects enabling or disabling of interrupt generation when TCFL overflows. 0: TCFL overflow interrupt request is disabled 1: TCFL overflow interrupt request is enabled
0
CCLRL
0
R/W
Counter Clear L Selects whether TCFL is cleared when TCFL and OCRFL match. 0: TCFL clearing by compare match is disabled 1: TCFL clearing by compare match is enabled
Note:
*
Only 0 can be written to clear the flag.
12.4
Operation
The timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in the output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. The timer F can also be used as two independent 8-bit timers. 12.4.1 Timer F Operation
The timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each of these modes is described below. (1) Operation in 16-Bit Timer Mode
When the CKSH2 bit is cleared to 0 in TCRF, the timer F operates as a 16-bit timer. Following a reset, TCF is initialized to H'0000, OCRF to H'FFFF, and TCRF and TCSRF to H'00. The counter is incremented by an input signal from an external event (TMIF pin). The TMIFEG bit in IEGR selects which edge of an external event is used for counting. The timer F counter input clock can be selected from internal clocks or external events according to settings of bits CKSL2 to CKSL0 in TCRF.
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Section 12 Timer F
OCRF contents are constantly compared with TCF, and when both values satisfy the compare match condition, CMFH is set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU, and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared. The output level of the TMOFH pin can be set by the TOLH bit in TCRF. When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU. (2) Operation in 8-Bit Timer Mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1, TCFH/TCFL is cleared. The output level of the TMOFH pin/TMOFL pin can be set by TOLH/TOLL in TCRF. When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is sent to the CPU.
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Section 12 Timer F
12.4.2 (1)
TCF Increment Timing
Internal Clock Operation
TCF is incremented by internal clock or external event input. Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of internal clock sources (/32, /16, /4, or W/4) created by dividing the system clock ( or W).
Count input clock (/4)
N-1
TCF
N
N+1
Figure 12.2 Count Timing for Internal Clock Operation (2) External Event Operation
When the CKSL2 bit in TCRF is cleared to 0, external event input is selected. The counter is incremented at both rising and falling edges of external events. The TMIFEG bit in IEGR selects which edge of an external event is used for counting. The external event pulse width requires clock time longer than 2 system clocks (), or 2 subclocks (SUB), depending on the operating mode. Note that an external event does not operate correctly with the lower pulse width.
TMIF (TMIFEG = 1)
Count input clock TCF
N-1
N
Figure 12.3 Count Timing for External Event Operation
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Section 12 Timer F
12.4.3
TMOFH/TMOFL Output Timing
In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is toggled by the occurrence of a compare match. Figure 12.4 shows the output timing.
Count input clock (/4)
TCF
N-1
N
0
OCRF Compere match signal
N
TMOFH, TMOFL
Figure 12.4 TMOFH/TMOFL Output Timing 12.4.4 TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
Count input clock (/4)
TCF
N-1
N
0
OCRF Compare match signal
N
Figure 12.5 TCF Clear Timing
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Section 12 Timer F
12.4.5
Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000. 12.4.6 Compare Match Flag Set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value). When TCF matches OCRF, the compare match signal is not generated until the next counter clock.
Count input clock (/4)
TCF
N-1
N
N+1
OCRF
N
Compare match signal
CMFH, CMFL
Figure 12.6 Compare Match Flag Set Timing
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Section 12 Timer F
12.5
Timer F Operating States
The timer F operating states are shown in table 12.2. Table 12.2 Timer F Operating States
Operating Mode
TCF
Reset
Reset
Active
Sleep
Watch
Sub-active Sub-sleep Standby
Halted* Functioning Functioning Functioning Halted* Retained Retained Retained Retained Retained Retained
Module Standby
Halted
Functioning* Functioning* Functioning/ Functioning/ Functioning/ Halted Halted*
OCRF TCRF TCSRF
Reset Reset Reset
Functioning Functioning Functioning
Retained Retained Retained
Retained Retained Retained
Retained Retained Retained
Note:
*
When W/4 is selected as the TCF input clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/ (s). When the counter is operated in subactive mode, watch mode, or subsleep mode, W /4 must be selected as the internal clock. The counter will not operate if any other internal clock is selected.
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Section 12 Timer F
12.6
Usage Notes
The following types of contention and operation can occur when the timer F is used. 12.6.1 16-Bit Timer Mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin should be used as a port pin. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, there is a probability of a compare match signal being generated and not being generated. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated. Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied. When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. 12.6.2 (1) 8-Bit Timer Mode
TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write. If an OCRFH write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, even if the written data and the counter value match, there is a probability of a compare match signal being generated and not being generated. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not output.
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Section 12 Timer F
(2)
TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, even if the written data and the counter value match, there is a probability of a compare match signal being generated and not being generated. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped. If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not output. 12.6.3 Flag Clearing
When W/4 is selected as the internal clock, "Interrupt source generation signal" will be operated with W and the signal will be outputted with W width. And, "Overflow signal" and "Compare match signal" are controlled with 2 cycles of W signals. Those signals are output with 2-cycle width of W (figure 12.7) In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of "Interrupt source generation signal", same interrupt request flag is set. (1 in figure 12.7) And, the timer overflow flag and compare match flag cannot be cleared during the term of validity of "Overflow signal" and "Compare match signal". For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer FH, timer FL interrupt might be repeated. (2 in figure 12.7) Therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register F (TCSRF) after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of RTE instruction when MULXS, DIVXS instruction is not used, 24 states when MULXS, DIVXS instruction is used) In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear.
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Section 12 Timer F
The term of validity of "Interrupt source generation signal" = 1 cycle of W + waiting time for completion of executing instruction + interrupt time synchronized with = 1/W + ST x (1/) + (2/) (second).....(1) ST: Executing number of execution states Method 1 is recommended to operate for time efficiency. Method 1 1. 2. 3. 4. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. After reading the timer control status register F (TCSRF), clear the timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). Enable interrupts (set IENFH, IENFL to 1).
Method 2 1. 2. 3. Set interrupt handling routine time to more than time that calculated with (1) formula. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16-bit mode and 8-bit mode.
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Section 12 Timer F
Interrupt request flag clear 2 Program processing Interrupt
Interrupt request flag clear Normal
Interrupt
W
Interrupt source generation signal (internal signal, nega-active) Overflow signal, compare match signal (internal signal, nega-active) Interrupt request flag (IRRTFH, IRRTFL) 1
Figure 12.7 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid 12.6.4 Timer Counter (TCF) Read/Write
When the internal clock W/4 is selected as the counter input clock in active (high-speed, mediumspeed) mode, normal write is not performed on TCF. And when reading TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of 1. In subactive mode, even if W/4 is selected as the input clock, TCF can be read from or written to normally.
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Section 12 Timer F
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Section 13 Timer G
Section 13 Timer G
Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceller, enabling accurate measurement of the input capture input signal duty cycle. If input capture input is not set, timer G functions as an 8-bit interval timer.
13.1
Features
* Choice of four internal clock sources (/64, /32, /2, W/4) * Dedicated input capture functions for rising and falling edges * Level detection at counter overflow It is possible to detect whether overflow occurred when the input capture input signal was high or when it was low. * Selection of whether or not the counter value is to be cleared at the input capture input signal rising edge, falling edge, or both edges * Two interrupt sources: one input capture, one overflow. The input capture input signal rising or falling edge can be selected as the interrupt source. * A built-in noise canceller eliminates high-frequency component noise in the input capture input signal. * Watch mode, subactive mode, or subsleep mode operation is possible when W/4 is selected as the internal clock. * Module standby mode enables this module to be placed in standby mode independently when it is not in use (for details, see section 6.4, Module Standby Function).
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Section 13 Timer G
PSS
TMG
W/4 ICRGF
TMIG
Noise canceler
Edge detector
TCG
NCS
ICRGR
IRRTG [Legend] TMG: TCG: ICRGF: ICRGR: IRRTG: NCS: PSS: Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer G interrupt request flag Noise canceler select Prescaler S
Figure 13.1 Block Diagram of Timer G
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Internal data bus
Level detector
Section 13 Timer G
13.2
Input/Output Pins
Table 13.1 shows the timer G pin configuration. Table 13.1 Pin Configuration
Pin Name Input capture input Abbreviation TMIG I/O Input Function Input capture input pin
13.3
Register Descriptions
The timer G has the following registers. For details on the clock halt register 3 (CKSTPR3), see section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3). * Timer counter G (TCG) * Input capture register GF (ICRGF) * Input capture register GR (ICRGR) * Timer mode register G (TMG) * Clock halt register 3 (CKSTPR3) 13.3.1 Timer Counter G (TCG)
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by bits CKS1 and CKS0 in TMG. TMIG in PMRF is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the rising edge, falling edge, or both edges of the input capture input signal, according to the setting made in TMG. When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details on interrupts, see section 4, Interrupt Controller. TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset. Note: An input capture signal may be generated when TMIG is modified.
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Section 13 Timer G
13.3.2
Input Capture Register GF (ICRGF)
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details on interrupts, see section 4, Interrupt Controller. To ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2 or 2SUB (when the noise canceller is not used). ICRGF is initialized to H'00 upon reset. 13.3.3 Input Capture Register GR (ICRGR)
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details on interrupts, see section 4, Interrupt Controller. To ensure dependable input capture operation, the pulse width of the input capture input signal must be at least 2 or 2SUB (when the noise canceller is not used). ICRGR is initialized to H'00 upon reset. 13.3.4 Timer Mode Register G (TMG)
TMG is an 8-bit readable/writable register that performs TCG clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags. TMG is initialized to H'00 upon reset.
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Section 13 Timer G
Bit 7
Bit Name OVFH
Initial Value 0
R/W
Description
R/(W)* Timer Overflow Flag H Indicates that TCG has overflowed from H'FF to H'00 when the input capture input signal is high. This flag is set by hardware and cleared by software. It cannot be set by software. [Setting condition] Set when input capture input signal is high level and TCG overflows from H'FF to H'00 [Clearing condition] Writing 0 to OVFH after reading OVFH = 1
6
OVFL
0
R/(W)* Timer Overflow Flag L Indicates that TCG has overflowed from H'FF to H'00 when the input capture input signal is low, or in interval operation. This flag is set by hardware and cleared by software. It cannot be set by software. [Setting condition] Set when TCG overflows from H'FF to H'00 while input capture input signal is low level or during interval operation [Clearing condition] Writing 0 to OVFL after reading OVFL = 1
5
OVIE
0
R/W
Timer Overflow Interrupt Enable Selects enabling or disabling of interrupt generation when TCG overflows. 0: TCG overflow interrupt request is disabled 1: TCG overflow interrupt request is enabled
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Section 13 Timer G
Bit 4
Bit Name IIEGS
Initial Value 0
R/W R/W
Description Input Capture Interrupt Edge Select Selects the input capture input signal edge that generates an interrupt request. 0: Interrupt generated on rising edge of input capture input signal 1: Interrupt generated on falling edge of input capture input signal
3 2
CCLR1 CCLR0
0 0
R/W R/W
Counter Clear 1 and 0 Specify whether or not TCG is cleared by the rising edge, falling edge, or both edges of the input capture input signal. 00: TCG clearing is disabled 01: TCG cleared by falling edge of input capture input signal 10: TCG cleared by rising edge of input capture input signal 11: TCG cleared by both edges of input capture input signal
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select Select the clock input to TCG from four internal clock sources. 00: Internal clock: counting on /64 01: Internal clock: counting on /32 10: Internal clock: counting on /2 11: Internal clock: counting on W/4
Note:
*
Only 0 can be written to clear the flag.
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Section 13 Timer G
13.3.5
Clock Halt Register 3 (CKSTPR3)
For details on placing timer G in and taking it out of module standby mode (this is controlled by the TGCKSTP bit in CKSTPR3) see section 6.1.4, Clock Halt Registers 1 to 3 (CKSTPR1 to CKSTPR3).
13.4
Noise Canceller
The noise canceller consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceller is set by NCS* in PMRF. Figure 13.2 shows a block diagram of the noise canceller.
Sampling clock
Input capture input signal
D
C Q Latch D
C Q Latch D
C Q Latch D
C Q Latch D
C Q Latch
Match detector
Noise canceler output
t Sampling clock
t: Set by CKS1 and CKS0
Figure 13.2 Noise Canceller Block Diagram
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Section 13 Timer G
The noise canceller consists of five latch circuits connected in series and a match detector circuit. When the noise cancellation function is not used (NCS = 0), the system clock is selected as the sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If all the outputs do not match, the previous value is retained. After a reset, the noise canceller output is initialized when the falling edge of the input capture input signal has been sampled five times. Therefore, after making a setting for use of the noise cancellation function, a pulse with at least five times the width of the sampling clock is a dependable input capture signal. Even if noise cancellation is not used, an input capture input signal pulse width of at least 2 or 2SUB is necessary to ensure that input capture operations are performed properly. Note: * An input capture signal may be generated when the NCS bit is modified. Figure 13.3 shows an example of noise canceller timing. In this example, high-level input of not more than five times the width of the sampling clock at the input capture input pin is eliminated as noise.
Input capture input signal
Sampling clock
Noise canceler output Eliminated as noise
Figure 13.3 Noise Canceller Timing (Example)
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Section 13 Timer G
13.5
Operation
Timer G is an 8-bit timer with built-in input capture and interval functions. 13.5.1 Timer G Functions
Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below. (1) Input Capture Timer Operation
When the TMIG bit in the port mode register F (PMRF) is set to 1, timer G functions as an input capture timer*. Upon reset, the timer mode register G (TMG), timer counter G (TCG), input capture register GF (ICRGF), and input capture register GR (ICRGR) are all initialized to H'00. Following a reset, TCG starts counting on the /64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. When a rising edge/falling edge is detected in the input capture signal input from the TMIG pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected by IIEGS in TMG is input, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. For details on interrupts, see section 4, Interrupt Controller. TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal, according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the input capture signal is high, the OVFH bit in TMG is set; if TCG overflows when the input capture signal is low, the OVFL bit in TMG is set. If the OVIE bit in TMG is 1 when these bits are set, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1, timer G sends an interrupt request to the CPU. For details on interrupts, see section 4, Interrupt Controller. Timer G has a built-in noise canceller that enables high-frequency component noise to be eliminated from pulses input from the TMIG pin. For details, see section 13.4, Noise Canceller. Note: * An input capture signal may be generated when TMIG is modified.
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Section 13 Timer G
(2)
Interval Timer Operation
When the TMIG bit in PMRF is cleared to 0, timer G functions as an interval timer. Following a reset, TCG starts counting on the /64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit in TMG is set to 1. If the OVIE bit in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1, timer G sends an interrupt request to the CPU. For details on interrupts, see section 4, Interrupt Controller. 13.5.2 Count Timing
TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four internal clock sources (/64, /32, /2, or W/4) created by dividing the system clock () or watch clock (W). 13.5.3 (1) Input Capture Input Timing
Without Noise Cancellation Function
For input capture input, dedicated input capture functions are provided for rising and falling edges. Figure 13.4 shows the timing for rising/falling edge input capture input.
Input capture input signal Input capture signal F Input capture signal R
Figure 13.4 Input Capture Input Timing (without Noise Cancellation Function)
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Section 13 Timer G
(2)
With Noise Cancellation Function
When noise cancellation is performed on the input capture input, the passage of the input capture signal through the noise canceller results in a delay of five sampling clock cycles from the input capture input signal edge. Figure 13.5 shows the timing in this case.
Input capture input signal
Sampling clock
Noise canceler output
Input capture signal R
Figure 13.5 Input Capture Input Timing (with Noise Cancellation Function) 13.5.4 Timing of Input Capture by Input Capture Input
Figure 13.6 shows the timing of input capture by input capture input.
Input capture signal TCG Input capture register
N-1 N N+1
H'xx
N
Figure 13.6 Timing of Input Capture by Input Capture Input
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Section 13 Timer G
13.5.5
TCG Clear Timing
TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 13.7 shows the timing for clearing by both edges.
Input capture input signal Input capture signal F Input capture signal R
TCG
N
H'00
N'
H'00
Figure 13.7 TCG Clear Timing
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Section 13 Timer G
13.6
Timer G Operation Modes
Timer G operation modes are shown in table 13.2. Table 13.2 Timer G Operation Modes
Module Operation Mode TCG Reset Active Functioning*
1
Sleep
1
Watch
Subactive
Subsleep
Standby
Standby Halted
Input capture Reset
Functioning* Functioning/ Functioning/ halted*
2
Functioning/h Halted alted*
3
halted*
3
Interval
Reset
Functioning*
1
1 Functioning* Functioning/ Functioning/
Functioning/h Halted alted*
3
Halted
halted* ICRGF Reset Functioning*
1
2
halted*
3
1 Functioning* Functioning/ Functioning/
Functioning/h Retained alted*3 Functioning/h Retained alted*
3
Retained
halted* ICRGR Reset Functioning*
1
2
halted*3
1 Functioning* Functioning/ Functioning/
Retained
halted* TMG Reset Functioning Retained
2
halted*
3
Retained
Functioning
Retained
Retained
Retained
Note:
1. When W/4 is selected as the TCG internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. This results in a maximum count cycle error of 1/(s). 2. When W/4 is selected as the TCG internal clock in watch mode, TCG and the noise canceller operate on the W/4 internal clock without regard to the SUB subclock (W/8, W/4, W/2). Note that when another internal clock is selected, TCG and the noise canceller do not operate, and input of the input capture input signal does not result in input capture. 3. To operate the timer G in subactive mode or subsleep mode, select W/4 as the TCG internal clock and W/2 as the subclock SUB. Note that when other internal clock is selected, or when W/8 or W/4 is selected as the subclock SUB, TCG and the noise canceller do not operate.
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Section 13 Timer G
13.7
13.7.1
Usage Notes
Internal Clock Switching and TCG Operation
Depending on the timing, TCG may be incremented by a switch between different internal clock sources. Table 13.3 shows the relation between internal clock switchover timing (by write to bits CKS1 and CKS0) and TCG operation. When TCG is internally clocked, an increment pulse is generated on detection of the falling edge of an internal clock signal, which is divided from the system clock () or subclock (W). For this reason, in a case like No.3 in table 13.3 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCG to increment. Table 13.3 Internal Clock Switching and TCG Operation
No. 1 Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from low level to low level TCG Operation
Clock before switching Clock after switching
Count clock
TCG
N
N+1
Write to CKS1 and CKS0
2
Goes from low level to high level
Clock before switching Clock after switching
Count clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
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Section 13 Timer G
No. 3
Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from high level to low level
TCG Operation
Clock before switching Clock after switching *
Count clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
4
Goes from high level to high level
Clock before switching Clock after switching
Count clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
Note:
*
The switchover is seen as a falling edge, and TCG is incremented.
13.7.2
Notes on Port Mode Register Modification
The following points should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceller function. * Switching input capture input pin function Note that when the pin function is switched by modifying TMIG in the port mode register F (PMRF), which performs input capture input pin control, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. Input capture input signal input edges, and the conditions for their occurrence, are summarized in table 13.4.
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Section 13 Timer G
Table 13.4 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching, and Conditions for Their Occurrence
Input Capture Input Signal Input Edge Generation of rising edge Conditions TMIG is modified from 0 to 1 while the TMIG pin is high NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceller Generation of falling edge TMIG is modified from 1 to 0 while the TMIG pin is high NCS is modified from 0 to 1 while the TMIG pin is low, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceller NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 1 to 0 after the signal is sampled five times by the noise canceller Note: When the PF0 pin is not set as an input capture input pin, the timer G input capture input signal is low.
* Switching input capture input noise canceller function When performing noise canceller function switching by modifying NCS in the port mode register F (PMRF), which controls the input capture input noise canceller, TMIG should first be cleared to 0. Note that if NCS is modified without first clearing TMIG, an edge will be regarded as having been input at the pin even though no valid edge has actually been input. Input capture input signal input edges, and the conditions for their occurrence, are summarized in table 13.5. Table 13.5 Input Capture Input Signal Input Edges Due to Noise Canceller Function Switching, and Conditions for Their Occurrence
Input Capture Input Signal Input Edge Generation of rising edge Conditions TMIG pin is modified from 0 to 1 while TMIG is 1, then NCS is modified from 0 to 1 before the signal is sampled five times by the noise canceller TMIG pin is modified from 1 to 0 while TMIG is 1, then NCS is modified from 1 to 0 before the signal is sampled five times by the noise canceller
Generation of falling edge
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Section 13 Timer G
When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 13.8 shows the procedure for handling of the port mode register and clearing of the interrupt request flag. When switching the pin function, set the interrupt-disabled state before handling the port mode register, then, after the port mode register operation has been performed, wait for the time required to confirm the input capture input signal as an input capture signal (at least two system clocks when the noise canceller is not in use; at least five sampling clocks when the noise canceller is used), before clearing the interrupt enable flag to 0. There are two ways of preventing interrupt request flag setting when the pin function is switched: by controlling the pin level so that the conditions shown in tables 13.4 and 13.5 are not satisfied, or by setting the opposite of the generated edge in the IIEGS bit in TMG.
Disable interrupts. (Interrupts can also be disabled by manipulating the interrupt enable bit in interrupt enable register 2.) After manipulating the port mode register, wait for the TMIG confirmation time* (at least two system clocks when the noise canceler is not used; at least five sampling clocks when the noise canceler is used), then clear the interrupt enable flag to 0.
Set I bit in CCR to 1
Manipulate port mode register *TMIG confirmation time Clear interrupt request flag to 0
Clear I bit in CCR to 0
Enable interrupts
Figure 13.8 Port Mode Register Manipulation and Interrupt Enable Flag Clearing Procedure
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Section 13 Timer G
13.8
Timer G Application Example
Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1. Figure 13.9 shows an example of the operation in this case.
Input capture input signal H'FF Input capture register GF Input capture register GR H'00
TCG
Counter cleared
Figure 13.9 Timer G Application Example
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Section 14 16-Bit Timer Pulse Unit (TPU)
Section 14 16-Bit Timer Pulse Unit (TPU)
Microcontrollers of the H8/38099 Group have an on-chip 16-bit timer pulse unit (TPU) that comprises two 16-bit timer channels. The function list of the TPU is shown in table 14.1. A block diagram of the TPU is shown in figure 14.1.
14.1
Features
* Maximum 4-pulse input/output * Selection of 7 or 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register synchronous input/output is possible by synchronous counter operation PWM output with any duty level is possible A maximum 3-phase PWM output is possible in combination with synchronous operation * Operation with cascaded connection * Fast access via internal 16-bit bus * 6-type interrupt sources * Module standby mode enables this module to be placed in standby mode independently when it is not in use (for details, refer to section 6.4, Module Standby Function).
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.1 TPU Functions
Item Count clock Channel 1 /1 /4 /16 /64 /256 TCLKA TCLKB General registers (TGR) I/O pins Counter clear function Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode Interrupt sources TGRA_1 TGRB_1 TIOCA1 TIOCB1 TGR compare match or input capture Available Available Available Available Available Available 3 sources * * * Compare match or input capture 1A Compare match or input capture 1B Overflow Channel 2 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOCA2 TIOCB2 TGR compare match or input capture Available Available Available Available Available Available 3 sources * * * Compare match or input capture 2A Compare match or input capture 2B Overflow
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Section 14 16-Bit Timer Pulse Unit (TPU)
Clock input Internal clock: /1
/4 /16 /64 /256 /1024 TCLKA TCLKB TCLKC
TSYR
Control logic
Internal data bus
TMDR
Channel 2
TSR
TSTR
External clock:
Common
TGRA
Control logic for channels 1 and 2
TIOR
TIER
TCR
Module data bus
TGRB
TCNT
Bus interface
Input/output pins Channel 1: Channel 2:
TIOCA1 TIOCB1 TIOCA2 TIOCB2
TIOR
[Legend] TSTR: Timer start register TSYR: Timer synchro register TCR: Timer control register TMDR: Timer mode register TCNT: Timer counter
TIOR: Timer I/O control registers TIER: Timer interrupt enable register TSR: Timer status register TGR (A, B): TImer general registers (A, B)
Figure 14.1 Block Diagram of TPU
14.2
Input/Output Pins
Table 14.2 Pin Configuration
Channel Common Symbol TCLKA TCLKB TCLKC 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 I/O Input Input Input I/O I/O I/O I/O Function External clock A input pin External clock B input pin External clock C input pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin
TIER
TCR
Interrupt request signals Channel 1: TGI1A TGI1B TCI1V Channel 2: TGI2A TGI2B TCI2V
TMDR
Channel 1
TSR
TGRA
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TGRB
TCNT
Section 14 16-Bit Timer Pulse Unit (TPU)
14.3
Register Descriptions
The TPU has the following registers for each channel. Channel 1: * Timer control register_1 (TCR_1) * Timer mode register_1 (TMDR_1) * Timer I/O control register_1 (TIOR_1) * Timer interrupt enable register_1 (TIER_1) * Timer status register_1 (TSR_1) * Timer counter_1 (TCNT_1) * Timer general register A_1 (TGRA_1) * Timer general register B_1 (TGRB_1) Channel 2: * Timer control register_2 (TCR_2) * Timer mode register_2 (TMDR_2) * Timer I/O control register_2 (TIOR_2) * Timer interrupt enable register_2 (TIER_2) * Timer status register_2 (TSR_2) * Timer counter_2 (TCNT_2) * Timer general register A_2 (TGRA_2) * Timer general register B_2 (TGRB_2) Common: * Timer start register (TSTR) * Timer synchro register (TSYR)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.1
Timer Control Register (TCR)
TCR controls TCNT operation for each channel. The TPU has a total of two TCR registers, one for each channel. TCR should be set when TCNT operation is stopped.
Bit 7 6 5 4 3 Bit Name CCLR1 CCLR0 CKEG1 CKEG0 Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved This bit is always read as 0 and cannot be modified. Counter Clear 1 and 0 These bits select the TCNT counter clearing source. See table 14.3 for details. Clock Edge 1 and 0 These bits select the input clock edge. When the internal clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). Internal clock edge selection is valid when the input clock is /4 or slower. If the input clock is /1, this setting is ignored and count at a rising edge is selected. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges [Legend] x: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Timer Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables14.4 and 14.5 for details.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.3 CCLR1 and CCLR0 (Channels 1 and 2)
Channel 1, 2 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note:
*
Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
Table 14.4 TPSC2 to TPSC0 (Channel 1)
Bit 2 Channel TPSC2 1 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT_2 overflow
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.5 TPSC2 to TPSC0 (Channel 2)
Bit 2 Channel TPSC2 2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024
14.3.2
Timer Mode Register (TMDR)
TMDR sets the operating mode for each channel. The TPU has a total of two TMDR registers, one for each channel. TMDR should be set when TCNT operation is stopped.
Bit 7, 6 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5, 4 All 0 Reserved These bits are always read as 0 and cannot be modified. 3, 2 1 0 MD1 MD0 All 0 0 0 R/W R/W Reserved The write value should always be 0. Modes 1 and 0 These bits set the timer operating mode. See table 14.6 for details.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.6 MD1 to MD0
Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 Description Normal operation Reserved PWM mode 1 PWM mode 2
14.3.3
Timer I/O Control Register (TIOR)
TIOR controls TGR. The TPU has a total of two TIOR registers, one for each channel. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. * TIOR_1, TIOR_2
Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 All 0 Initial Value All 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRA. For details, refer to tables 14.9 and 14.10. Description I/O Control B3 to B0 Specify the function of TGRB. For details, refer to tables 14.7 and 14.8.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.7 TIOR_1 (Channel 1)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is TIOCB1 pin register Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge Capture input source is TIOCB1 pin Input capture at both edges Setting prohibited
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.8 TIOR_2 (Channel 2)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is TIOCB2 pin register Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge Capture input source is TIOCB2 pin Input capture at both edges
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.9 TIOR_1 (Channel 1)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 [Legend] x: Don't care x x x Input capture register TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge Capture input source is TIOCA1 pin Input capture at both edges Setting prohibited
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.10 TIOR_2 (Channel 2)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 0 1 1 [Legend] x: Don't care x TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is TIOCA2 pin register Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge Capture input source is TIOCA2 pin Input capture at both edges
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.4
Timer Interrupt Enable Register (TIER)
TIER controls enabling or disabling of interrupt requests for each channel. The TPU has a total of two TIER registers, one for each channel.
Bit 7 6 5 4 Bit Name TCIEV Initial Value 0 1 0 0 R/W R/W R/W Description Reserved This bit is readable/writable. Reserved This bit is always read as 1 and cannot be modified. Reserved The write value should always be 0. Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3, 2 All 0 Reserved These bits are always read as 0 and cannot be modified. 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.5
Timer Status Register (TSR)
TSR indicates the status for each channel. The TPU has a total of two TSR registers, one for each channel.
Bit 7, 6 5 4 Bit Name TCFV Initial Value All 1 0 0 R/W Description Reserved These bits are always read as 1 and cannot be modified. Reserved This bit is always read as 0 and cannot be modified. R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. [Setting condition] The TCNT value overflows (changes from H'FFFF to H'0000 ) [Clearing condition] Writing of 0 to bit TCFV after reading TCFV = 1 3, 2 1 TGFB All 0 0 Reserved These bits are always read as 0 and cannot be modified. R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * TCNT = TGRB and TGRB is functioning as output compare register The TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register Writing of 0 to bit TGFB after reading TGFB = 1
[Clearing condition] *
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Section 14 16-Bit Timer Pulse Unit (TPU)
Bit 0
Bit Name TGFA
Initial value 0
R/W
Description
R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * * TCNT = TGRA and TGRA is functioning as output compare register The TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register Writing of 0 to bit TGFA after reading TGFA = 1
[Clearing condition] * Note: * Only 0 can be written to clear the flag.
14.3.6
Timer Counter (TCNT)
TCNT is a 16-bit readable/writable counter. The TPU has a total of two TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in standby mode. TCNT cannot be accessed in 8-bit units; it must always be accessed in 16-bit units. 14.3.7 Timer General Register (TGR)
TGR is a 16-bit readable/writable register, functioning as either output compare or input capture register. The TPU has a total of four TGR registers, two for each channel. TGR is initialized to H'FFFF by a reset. TGR cannot be accessed in 8-bit units; it must always be accessed in 16-bit units.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.8
Timer Start Register (TSTR)
TSTR selects TCNT operation/stoppage for channels 1 and 2. TCNT starts counting for channel in which the corresponding bit is set to 1. When setting the operating mode in TMDR or setting the TCNT count clock in TCR, first stop the TCNT operation.
Bit 7 to 3 2 1 Bit Name CST2 CST1 Initial Value All 0 0 0 R/W R/W R/W R/W Description Reserved The write value should always be 0. Counter Start 2 and 1 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the output compare output level of the TIOC pin is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_n count operation is stopped 1: TCNT_n performs count operation [Legend] n = 2 or 1 0 0 R/W Reserved The write value should always be 0.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.9
Timer Synchro Register (TSYR)
TSYR selects independent operation or synchronous operation of TCNT for each channel. Synchronous operation is performed for channel in which the corresponding bit in TSYR is set to 1.
Bit 7 to 3 2 1 Bit Name SYNC2 SYNC1 Initial Value All 0 0 0 R/W R/W R/W R/W Description Reserved The write value should always be 0. Timer Synchro 2 and 1 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR1 and CCLR0 in TCR. 0: TCNT_n operates independently (TCNT presetting/ clearing is unrelated to other channels) 1: TCNT_n performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible [Legend] n = 2 or 1 0 0 R/W Reserved The write value should always be 0.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.4
14.4.1
Interface to CPU
16-Bit Registers
TCNT and TGR are 16-bit registers. As the data bus to the CPU is 16 bits wide, these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 14.2.
Internal data bus H
CPU
L
Bus interface
Module data bus
Upper 8 bits TCNT
Lower 8 bits
Figure 14.2 16-Bit Register Access Operation [CPU TCNT (16 Bits)] 14.4.2 8-Bit Registers
Registers other than TCNT and TGR are 8-bit. They can be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figure 14.3 and 14.4.
Internal data bus H
CPU
L
Bus interface
Module data bus
TCR
Figure 14.3 8-Bit Register Access Operation [CPU TCR (Upper 8 Bits)]
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Section 14 16-Bit Timer Pulse Unit (TPU)
Internal data bus H
CPU
L
Bus interface
Module data bus
TMDR
Figure 14.4 8-Bit Register Access Operation [CPU TMDR (Lower 8 Bits)]
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.5
14.5.1
Operation
Basic Functions
Each channel has TCNT and TGR. TCNT performs up-counting, and is also capable of freerunning operation, periodic counting, and external event counting. TGR can be used as an input capture register or output compare register. (1) Counter Operation
When one of bits CST1 and CST2 is set to 1 in TSTR, TCNT for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. (a) Example of Count Operation Setting Procedure
Figure 14.5 shows an example of the count operation setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select TGR to be used as the TCNT clearing source with bits CCLR1 and CCLR0 in TCR. [3] Designate TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation.
Operation selection
Select counter clock
[1]
Periodic counter
Free-running counter
Select counter clearing source
[2]
[3] Select output compare register
Set period
[4]
Start count operation
[5]
Start count operation
Figure 14.5 Example of Counter Operation Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(b)
Free-Running Count Operation and Periodic Count Operation
Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 14.6 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000 CST bit TCFV
Time
Figure 14.6 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, TCNT for the relevant channel performs periodic count operation. TGR for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 and CCLR1 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Figure 14.7 illustrates periodic counter operation.
TCNT value TGR
Counter cleared by TGR compare match
H'0000 CST bit TGF
Time
Flag cleared by software
Figure 14.7 Periodic Counter Operation (2) Waveform Output by Compare Match
The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match
Figure 14.8 shows an example of the setting procedure for waveform output by compare match.
[1] Select 0 output or 1 output for initial value, and 0 output, 1 output, or toggle output, by for compare match output value means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Input selection
[1]
Select waveform output mode
[2]
Set output timing
[3]
Start count operation
< Waveform output >
Figure 14.8 Example of Setting Procedure for Waveform Output by Compare Match
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Section 14 16-Bit Timer Pulse Unit (TPU)
(b)
Examples of Waveform Output Operation
Figure 14.9 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time
Figure 14.9 Example of 0 Output/1 Output Operation Figure 14.10 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output
TIOCB TIOCA
Figure 14.10 Example of Toggle Output Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
(3)
Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. (a) Example of Input Capture Operation Setting Procedure
Figure 14.11 shows an example of the setting procedure for input capture operation.
Input selection
Select input capture input
[1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and, rising edge, falling edge, or both edges as the input signal edge. [1] [2] Set the CST bit in TSTR to 1 to start the count operation. [2]
Start count

Figure 14.11 Example of Setting Procedure for Input Capture Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
(b)
Example of Input Capture Operation
Figure 14.12 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the input capture input edge of the TIOCA pin, the falling edge has been selected as the input capture input edge of the TIOCB pin, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160
H'0010 H'0005 H'0000 Time
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB TGRB H'0180
Figure 14.12 Example of Input Capture Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.5.2
Synchronous Operation
In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Synchronous operation can be set for each channel. (1) Example of Synchronous Operation Setting Procedure
Figure 14.13 shows an example of the synchronous operation setting procedure.
Synchronous operation selection Set synchronous operation [1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2]
Clearing source generation channel? Yes Select counter clearing source Start count
No
[3]
Set synchronous counter clearing Start count
[4]
[5]
[5]

[1] Set 1 to the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR1 and CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR1 and CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set 1 to the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 14.13 Example of Synchronous Operation Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
Example of Synchronous Operation
Figure 14.14 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 1 and 2, TGRB_1 compare match has been set as the channel 1 counter clearing source, and synchronous clearing has been set for the channel 2 counter clearing source. Two-phase PWM waveforms are output from pins TIOC1A and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_1 compare match, are performed for channel 1 and 2 TCNT counters, and the data set in TGRB_1 is used as the PWM cycle. For details on PWM modes, see section 14.5.4, PWM Modes.
Synchronous clearing by TGRB_1 compare match TCNT_1 and TCNT_2 TGRB_1 TGRB_2 TGRA_1 TGRA_2 H'0000 Time
TIOCA1 TIOCA2
Figure 14.14 Example of Synchronous Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.5.3
Operation with Cascaded Connection
Operation as a 32-bit counter can be performed by cascading two 16-bit counter channels. This function is enabled when the TPSC2 to TPSC0 bits in TCR are set to count on TCNT2 overflow for the channel 1 counter clock. Table 14.11 shows the counter combination used in operation with the cascaded connection. Table 14.11 Counter Combination in Operation with Cascaded Connection
Combination Channel 1 and channel 2 Upper 16 bits TCNT1 Lower 16 bits TCNT2
(1)
Setting Procedure for Operation with Cascaded Connection
Figure 14.15 shows the setting procedure for cascaded connection operation.
Operation with cascaded connection Set operation with cascaded connection
[1] Set bits TPSC2 to TPSC0 in TCR in channel 1 to B'111 to select to count on TCNT2 overflow. [1] [2] Set 1 to the CST bit in TSTR corresponding the upper and lower channels to start counting.
Start count
[2]

Figure 14.15 Setting Procedure for Operation with Cascaded Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
Example of Operation with Cascaded Connection
Figure 14.16 shows an example of operation with cascaded connection, where TCNT1 is set to count TCNT2 overflow, TCRA_1 and TCRA_2 are set to be input capture registers, and the TIOC pin rising edge is selected. If rising edges are input simultaneously to the TIOCA1 and TIOCA2 pins, the upper 16 bits of 32bit data are transferred to TGRA_1 and the lower 16 bits are transferred to TGRA_2.
TCNT1 clock
TCNT1 TCNT2 clock
H'03A1
H'03A2
TCNT2
H'FFFF
H'0000
H'0001
TIOCA1 TIOCA2
TGRA_1
H'03A2
TGRA_2
H'0000
Figure 14.16 Example of Operation with Cascaded Connection
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.5.4
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. (1) PWM Mode 1
PWM output is generated from the TIOCA pin by pairing TGRA with TGRB. The level specified by bits IOA0 to IOA3 in TIOR is output from the TIOCA pin at compare match A, and the level specified by bits IOB0 to IOB3 in TIOR is output at compare match B. The initial output value is the value set in TGRA. If the set values of paired TGRs are identical, the output value does not change even if a compare match occurs. In PWM mode 1, PWM output is enabled up to 2 phases. (2) PWM Mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change even if a compare match occurs. In PWM mode 2, PWM output is enabled up to 3 phases. The correspondence between PWM output pins and registers is shown in table 14.12.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.12 PWM Output Registers and Output Pins
Output Pins Channel 1 Registers TGRA_1 TGRB_1 2 Note: * TGRA_2 TGRB_2 TIOCA2 PWM Mode 1 TIOCA1 PWM Mode 2* TIOCA1 TIOCB1 TIOCA2 TIOCB2
In PWM mode 2, PWM output is not possible for TGR in which the period is set.
(3)
Example of PWM Mode Setting Procedure
Figure 14.17 shows an example of the PWM mode setting procedure.
PWM mode
Select counter clock
[1]
Select counter clearing source
[2]
Select waveform output level
[3]
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR1 and CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation.
Set TGR
[4]
Set PWM mode
[5]
Start count
[6]

Figure 14.17 Example of PWM Mode Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(4)
Examples of PWM Mode Operation
Figure 14.18 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB are used as the duty levels.
TCNT value Counter cleared by TGRA compare match TGRA
TGRB H'0000 Time
TIOCA
Figure 14.18 Example of PWM Mode Operation (1)
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Section 14 16-Bit Timer Pulse Unit (TPU)
Figure 14.19 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 1 and 2, TGRB_2 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_1, TGRB_1, and TGRA_2), outputting a 3-phase PWM waveform. In this case, the value set in TGRB_2 is used as the cycle, and the values set in the other TGRs are used as the duty levels.
Synchronous clearing by TGRB_2 compare match TCNT_1 and TCNT_2 TGRB_2 TGRA_2 TGRB_1 TGRA_1 H'0000 Time
TIOCA1
TIOCB1
TIOCA2
Figure 14.19 Example of PWM Mode Operation (2) Figure 14.20 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
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Section 14 16-Bit Timer Pulse Unit (TPU)
(1) When the value of the duty register is larger than that of the cycle register
TCNT value TGRB rewritten
TGRA
TGRB H'0000
TGRB rewritten
TGRB rewritten Time
TIOCA
0% duty
(2) When the values of the duty and cycle registers are identical
Output does not change when cycle register and duty register compare matches occur simultaneously
TCNT value TGRB rewritten
TGRA
TGRB rewritten
TGRB H'0000
TGRB rewritten Time 100% duty
TIOCA
(3) When the value of the duty register is made larger than that of the cycle register, after the values of the duty and cycle registers are set identical TCNT value
TGRA Output does not change when cycle register and duty register compare matches occur simultaneously
TGRB rewritten TGRB rewritten
TGRB H'0000
TGRB rewritten Time 100% duty 0% duty
TIOCA
(4) When the value of the duty register is made smaller than that of TCNT, before duty register compare match occurs TCNT value
TGRA
TGRB rewritten
TGRB H'0000
Time
TIOCA
0% duty
Figure 14.20 Example of PWM Mode Operation (3)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.6
Interrupt Sources
There are two kinds of TPU interrupt source; TGR input capture/compare match and TCNT overflow. Each interrupt source has its own status flag and enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt source is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Mask levels within a channel can be changed by the interrupt controller. For details, see section 4, Interrupt Controller. Table 14.13 lists the TPU interrupt sources. Table 14.13 TPU Interrupts
Channel 1 Name TGI1A TGI1B TCI1V 2 TGI2A TGI2B TCI2V Interrupt Source TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow Interrupt Flag Priority TGFA_1 TGFB_1 TCFV_1 TGFA_2 TGFB_2 TCFV_2 Low High
(1)
Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has a total of four input capture/compare match interrupts, two for each channel. (2) Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has a total of two overflow interrupts, one for each channel.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.7
14.7.1 (1)
Operation Timing
Input/Output Timing
TCNT Count Timing
Figure 14.21 shows TCNT count timing in internal clock operation, and figure 14.22 shows TCNT count timing in external clock operation.
Internal clock
Falling edge
Rising edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 14.21 Count Timing in Internal Clock Operation
External clock
Falling edge
Rising edge
Falling edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 14.22 Count Timing in External Clock Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
Output Compare Output Timing
A compare match signal is generated in the last state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 14.23 shows output compare output timing.
TCNT input clock N N+1
TCNT
TGR
N
Compare match signal TIOC pin
Figure 14.23 Output Compare Output Timing
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Section 14 16-Bit Timer Pulse Unit (TPU)
(3)
Input Capture Signal Timing
Figure 14.24 shows input capture signal timing.
Input capture input Input capture signal
TCNT
N
N+1
N+2
TGR
N
N+2
Figure 14.24 Input Capture Input Signal Timing (4) Timing for Counter Clearing by Compare Match/Input Capture
Figure 14.25 shows the timing when counter clearing on compare match is specified, and figure 14.26 shows the timing when counter clearing on input capture is specified.
Compare match signal Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 14.25 Counter Clear Timing (Compare Match)
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Section 14 16-Bit Timer Pulse Unit (TPU)
Input capture signal
Counter clear signal
TCNT
N
H'0000
TGR
N
Figure 14.26 Counter Clear Timing (Input Capture) 14.7.2 (1) Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match
Figure 14.27 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing.
TCNT input clock TCNT N N+1
TGR Compare match signal TGF flag TGI interrupt
N
Figure 14.27 TGI Interrupt Timing (Compare Match)
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
TGF Flag Setting Timing in Case of Input Capture
Figure 14.28 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing.
Input capture signal TCNT N
TGR TGF flag TGI interrupt
N
Figure 14.28 TGI Interrupt Timing (Input Capture) (3) TCFV Flag Setting Timing
Figure 14.29 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing.
TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000
TCIV interrupt
Figure 14.29 TCIV Interrupt Setting Timing
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Section 14 16-Bit Timer Pulse Unit (TPU)
(4)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 14.30 shows the timing for status flag clearing by the CPU.
TSR write cycle T2 T1
Address Write signal Status flag
TSR address
Interrupt request signal
Figure 14.30 Timing for Status Flag Clearing by CPU
14.8
14.8.1
Usage Notes
Module Standby Function Setting
TPU operation can be disabled or enabled using the clock stop register. The initial setting is for the TPU to operate. Register access is enabled by clearing the module standby function. For details, refer to section 6.4, Module Standby Function. 14.8.2 Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.8.3
Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the last state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where (N + 1) f: Counter frequency : Operating frequency N: TGR set value Contention between TCNT Write and Clear Operation
14.8.4
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes priority and the TCNT write is not performed. Figure 14.31 shows the timing in this case.
TCNT write cycle T1 T2 Address Write signal Counter clear signal TCNT N H'0000 TCNT address
Figure 14.31 Contention between TCNT Write and Clear Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.8.5
Contention between TCNT Write and Increment Operation
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes priority and TCNT is not incremented. Figure 14.32 shows the timing in this case.
TCNT write cycle T1 T2 Address Write signal TCNT input clock TCNT N TCNT write data M TCNT address
Figure 14.32 Contention between TCNT Write and Increment Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.8.6
Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes priority and the compare match signal is inhibited. A compare match does not occur even if the previous value is written. Figure 14.33 shows the timing in this case.
TGR write cycle T2 T1 Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M Inhibited TGR address
Figure 14.33 Contention between TGR Write and Compare Match
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.8.7
Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, data that is read will be data after input capture transfer. Figure 14.34 shows the timing in this case.
TGR read cycle T2 T1 Address Read signal Input capture signal TGR Internal data bus X M M TGR address
Figure 14.34 Contention between TGR Read and Input Capture
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.8.8
Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes priority and the write to TGR is not performed. Figure 14.35 shows the timing in this case.
TGR write cycle T2 T1 Address Write signal Input capture signal TCNT M M TGR address
TGR
Figure 14.35 Contention between TGR Write and Input Capture
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.8.9
Contention between Overflow and Counter Clearing
If overflow and counter clearing occur simultaneously, the TCFV flag in TSR is not set and TCNT clearing takes priority. Figure 14.36 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR.
TCNT input clock TCNT Counter clear signal TGF TCFV Disabled H'FFFF H'0000
Figure 14.36 Contention between Overflow and Counter Clearing
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.8.10 Contention between TCNT Write and Overflow If there is an up-count in the T2 state of a TCNT write cycle and overflow occurs, the TCNT write takes priority and the TCFV flag in TSR is not set. Figure 14.37 shows the operation timing when there is contention between TCNT write and overflow.
TCNT write cycle T2 T1 Address Write signal TCNT TCFV flag H'FFFF M TCNT address
TCNT write data
Figure 14.37 Contention between TCNT Write and Overflow 14.8.11 Multiplexing of I/O Pins The TIOCA1 I/O pin is multiplexed with the TCLKA input pin, the TIOCB1 I/O pin with the TCLKB input pin, and the TIOCA2 I/O pin with the TCLKC input pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 14.8.12 Interrupts when Module Standby Function is Used If the module standby function is used when an interrupt has been requested, it will not be possible to clear the CPU interrupt source with the interrupt request enabled. Interrupts should therefore be disabled before using the module standby function. 14.8.13 Output Conditions for 0% Duty and 100% Duty When TGR is rewritten to change the duty in PWM mode, 0% duty or 100% duty is specified depending on the TCT value when rewritten, the TGR value before rewritten, and the TGR value after rewritten. For derails, refer to figure 14.20.
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Section 15 Asynchronous Event Counter (AEC)
Section 15 Asynchronous Event Counter (AEC)
The asynchronous event counter (AEC) is an event counter that is incremented by external event clock or internal clock input. Figure 15.1 shows a block diagram of the asynchronous event counter.
15.1
Features
* Can count asynchronous events Can count external events input asynchronously without regard to the operation of system clocks () or subclocks (SUB). * Can be used as two-channel independent 8-bit event counter or single-channel independent 16bit event counter. * Event/clock input is enabled when IRQAEC goes high or event counter PWM output (IECPWM) goes high. * Falling edge, rising edge, or both edges can be selected as the detected edge for IRQAEC or event counter PWM output (IECPWM) interrupts. When the asynchronous counter is not used, they can be used as independent interrupts. * When an event counter PWM is used, event clock input enabling/disabling can be controlled at a constant cycle. * Selection of four clock sources Three internal clocks (/2, /4, or /8) or external event can be selected. * Falling edge, rising edge, or both edge counting is possible for the AEVL and AEVH pins. * Counter resetting and halting of the count-up function can be controlled by software. * Automatic interrupt generation on detection of an event counter overflow * Module standby mode enables this module to be placed in standby mode independently when it is not in use (For details, refer to section 6.4, Module Standby Function).
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Section 15 Asynchronous Event Counter (AEC)
IRREC PSS ECCR ECCSR
/2 /4, /8 ECH (8 bits)
OVH AEVH Edge sensing circuit OVL
CK
AEVL IRQAEC
Edge sensing circuit Edge sensing circuit To CPU interrupt (IRREC2) ECPWCR
IECPWM
PWM waveform generator /2, /4, /8, /16, /32, /64 AEGSR [Legend] ECPWCR: ECPWDR: AEGSR: ECCSR: Event counter PWM compare register Event counter PWM data register Input pin edge select register Event counter control/status register ECL: ECCR: ECH: PSS: Event counter L Event counter control register Event counter H Prescaler S
ECPWDR
Figure 15.1 Block Diagram of Asynchronous Event Counter
15.2
Input/Output Pins
Table 15.1 shows the pin configuration of the asynchronous event counter. Table 15.1 Pin Configuration
Pin Name Abbreviation I/O Input Input Input Function Event input pin for input to event counter H Event input pin for input to event counter L Input pin for interrupt enabling event input
Asynchronous event AEVH input H Asynchronous event AEVL input L Event input enable interrupt input IRQAEC
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Internal data bus
ECL (8 bits)
CK
Section 15 Asynchronous Event Counter (AEC)
15.3
Register Descriptions
The asynchronous event counter has the following registers. * Event counter PWM compare register (ECPWCR) * Event counter PWM data register (ECPWDR) * Input pin edge select register (AEGSR) * Event counter control register (ECCR) * Event counter control/status register (ECCSR) * Event counter H (ECH) * Event counter L (ECL) 15.3.1 Event Counter PWM Compare Register (ECPWCR)
ECPWCR sets the one conversion period of the event counter PWM waveform. ECPWCR should be read from or written to in word units.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description One Conversion Period of Event Counter PWM Waveform When the ECPWME bit in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR should not be modified. When changing the conversion period, the event counter PWM must be halted by clearing the ECPWME bit in AEGSR to 0 before modifying ECPWCR.
ECPWCR15 1 ECPWCR14 1 ECPWCR13 1 ECPWCR12 1 ECPWCR11 1 ECPWCR10 1 ECPWCR9 ECPWCR8 ECPWCR7 ECPWCR6 ECPWCR5 ECPWCR4 ECPWCR3 ECPWCR2 ECPWCR1 ECPWCR0 1 1 1 1 1 1 1 1 1 1
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Section 15 Asynchronous Event Counter (AEC)
15.3.2
Event Counter PWM Data Register (ECPWDR)
ECPWDR controls data of the event counter PWM waveform generator. ECPWDR should be read from or written to in word units.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9 ECPWDR8 ECPWDR7 ECPWDR6 ECPWDR5 ECPWDR4 ECPWDR3 ECPWDR2 ECPWDR1 ECPWDR0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W W W W W W W W W W W W W W W W W Description Data Control of Event Counter PWM Waveform Generator When the ECPWME bit in AEGSR is 1, the event counter PWM is operating and therefore ECPWDR should not be modified. When changing the conversion cycle, the event counter PWM must be halted by clearing the ECPWME bit in AEGSR to 0 before modifying ECPWDR. The read value is undefined.
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Section 15 Asynchronous Event Counter (AEC)
15.3.3
Input Pin Edge Select Register (AEGSR)
AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins.
Bit 7 6 Bit Name AHEGS1 AHEGS0 Initial Value 0 0 R/W R/W R/W Description AEC Edge Select H Select rising, falling, or both edge sensing for the AEVH pin. 00: Falling edge on AEVH pin is sensed 01: Rising edge on AEVH pin is sensed 10: Both edges on AEVH pin are sensed 11: Setting prohibited 5 4 ALEGS1 ALEGS0 0 0 R/W R/W AEC Edge Select L Select rising, falling, or both edge sensing for the AEVL pin. 00: Falling edge on AEVL pin is sensed 01: Rising edge on AEVL pin is sensed 10: Both edges on AEVL pin are sensed 11: Setting prohibited 3 2 AIEGS1 AIEGS0 0 0 R/W R/W IRQAEC Edge Select Select rising, falling, or both edge sensing for the IRQAEC pin. 00: Falling edge on IRQAEC pin is sensed 01: Rising edge on IRQAEC pin is sensed 10: Both edges on IRQAEC pin are sensed 11: Setting prohibited 1 ECPWME 0 R/W Event Counter PWM Enable Controls operation of event counter PWM and selection of IRQAEC. 0: AEC PWM halted, IRQAEC selected 1: AEC PWM enabled, IRQAEC not selected 0 0 R/W Reserved This bit can be read from or written to. However, this bit should not be set to 1.
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Section 15 Asynchronous Event Counter (AEC)
15.3.4
Event Counter Control Register (ECCR)
ECCR controls the counter input clock and IRQAEC/IECPWM.
Bit 7 6 Bit Name ACKH1 ACKH0 Initial Value 0 0 R/W R/W R/W Description AEC Clock Select H Select the clock used by ECH. 00: AEVH pin input 01: /2 10: /4 11: /8 5 4 ACKL1 ACKL0 0 0 R/W R/W AEC Clock Select L Select the clock used by ECL. 00: AEVL pin input 01: /2 10: /4 11: /8 3 2 1 PWCK2 PWCK1 PWCK0 0 0 0 R/W R/W R/W Event Counter PWM Clock Select Select the event counter PWM clock. 000: /2 001: /4 010: /8 011: /16 1x0: /32 1x1: /64 When changing the event counter PWM clock, stop the PWM by setting the ECPWME bit in AEGSR to 0, and then change the value of these bits. 0 0 R/W Reserved This bit can be read from or written to. However, this bit should not be set to 1. [Legend] x: Don't care
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Section 15 Asynchronous Event Counter (AEC)
15.3.5
Event Counter Control/Status Register (ECCSR)
ECCSR controls counter overflow detection, counter resetting, and count-up function.
Bit 7 Bit Name OVH Initial Value 0 R/W R/(W)* Description Counter Overflow H This is a status flag indicating that ECH has overflowed. [Setting condition] ECH overflows from H'FF to H'00 [Clearing condition] Writing of 0 to bit OVH after reading OVH = 1 6 OVL 0 R/(W)* Counter Overflow L This is a status flag indicating that ECL has overflowed. [Setting condition] ECL overflows from H'FF to H'00 while CH2 is set to 1 [Clearing condition] Writing of 0 to bit OVL after reading OVL = 1 5 0 R/W Reserved Although this bit is readable/writable, it should not be set to 1. 4 CH2 0 R/W Channel Select Selects how ECH and ECL event counters are used 0: ECH and ECL are used together as a single-channel 16-bit event counter 1: ECH and ECL are used as two-channel 8-bit event counter 3 CUEH 0 R/W Count-Up Enable H Enables event clock input to ECH. 0: ECH event clock input is disabled (ECH value is retained) 1: ECH event clock input is enabled
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Section 15 Asynchronous Event Counter (AEC)
Bit 2
Bit Name CUEL
Initial Value 0
R/W R/W
Description Count-Up Enable L Enables event clock input to ECL. 0: ECL event clock input is disabled (ECL value is retained) 1: ECL event clock input is enabled
1
CRCH
0
R/W
Counter Reset Control H Controls resetting of ECH. 0: ECH is reset 1: ECH reset is cleared and count-up function is enabled
0
CRCL
0
R/W
Counter Reset Control L Controls resetting of ECL. 0: ECL is reset 1: ECL reset is cleared and count-up function is enabled
Note:
*
Only 0 can be written to clear the flag.
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Section 15 Asynchronous Event Counter (AEC)
15.3.6
Event Counter H (ECH)
ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. When word access is performed for ECH, the upper 8 bits and lower 8 bits of a 16-bit event counter can be read from in one bus cycle.
Bit 7 6 5 4 3 2 1 0 Bit Name ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVH pin, /2, /4, or /8, or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by the CRCH bit in ECCSR.
15.3.7
Event Counter L (ECL)
ECL is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECL also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECH. When word access is performed for ECL, the upper 8 bits and lower 8 bits of a 16-bit event counter can be read from in one bus cycle.
Bit 7 6 5 4 3 2 1 0 Bit Name ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVL pin, /2, /4, or /8 can be selected as the input clock source. ECL can be cleared to H'00 by the CRCL bit in ECCSR.
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Section 15 Asynchronous Event Counter (AEC)
15.4
15.4.1
Operation
16-Bit Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources--/2, /4, /8, or AEVL pin input--can be selected by means of bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0. Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 15.2 shows the software procedure when ECH and ECL are used as a 16-bit event counter.
Start
Clear CH2 to 0 Set ACKL1, ACKL0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 15.2 Software Procedure when Using ECH and ECL as 16-Bit Event Counter As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset, and as ACKL1 and ACKL0 are cleared to B'00, the operating clock is asynchronous event input from the AEVL pin (using falling edge sensing). When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
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Section 15 Asynchronous Event Counter (AEC)
15.4.2
8-Bit Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. /2, /4, /8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and /2, /4, /8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR. Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and with bits ALEGS1 and ALEGS0 when AEVL pin input is selected. Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 15.3 shows the software procedure when ECH and ECL are used as 8-bit event counters.
Start Set CH2 to 1 Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1, AHEGS0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 15.3 Software Procedure when Using ECH and ECL as 8-Bit Event Counters When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted. Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
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Section 15 Asynchronous Event Counter (AEC)
15.4.3
IRQAEC Operation
When the ECPWME bit in AEGSR is 0, the ECH and ECL input clocks are enabled when IRQAEC goes high. When IRQAEC goes low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually. IRQAEC can also operate as an interrupt source. Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIAGS1 and AIAGS0 in AEGSR. 15.4.4 Event Counter PWM Operation
When the ECPWME bit in AEGSR is 1, the ECH and ECL input clocks are enabled when event counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL cannot be controlled individually. IECPWM can also operate as an interrupt source. Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated, IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits AIAGS1 and AIAGS0 in AEGSR. Figure 15.4 and table 15.2 show examples of event counter PWM operation.
toff = T x (Ndr +1)
ton tcm = T x (Ncm +1)
ton: toff: tcm: T: Ndr:
Clock input enable time Clock input disable time One conversion period ECPWM input clock cycle Value of ECPWDR Fixed low when Ndr =H'FFFF Ncm: Value of ECPWCR
Figure 15.4 Event Counter Operation Waveform
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Section 15 Asynchronous Event Counter (AEC)
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this condition, the output of the event counter PWM is fixed low. Table 15.2 Examples of Event Counter PWM Operation Conditions: fosc = 4 MHz, f = 4 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11, ECPWDR value (Ndr) = H'16E3
Clock Source Selection /2 /4 /8 /16 /32 /64 Note: * Clock Source Cycle (T)* 0.5 s 1 s 2 s 4 s 8 s 16 s toff minimum width toff = T x ECPWDR ECPWCR Value (Ncm) Value (Ndr) (Ndr + 1) H'7A11 D'31249 H'16E3 D'5859 2.93 ms 5.86 ms 11.72 ms 23.44 ms 46.88 ms 93.76 ms tcm = T x (Ncm + 1) 15.625 ms 31.25 ms 62.5 ms 125.0 ms 250.0 ms 500.0 ms ton = tcm - toff 12.695 ms 25.39 ms 50.78 ms 101.56 ms 203.12 ms 406.24 ms
15.4.5
Operation of Clock Input Enable/Disable Function
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by the event counter PWM output, IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending on the IRQAEC or IECPWM timing. Figure 15.5 shows an example of the operation.
Input event
IRQAEC or IECPWM Edge generated by clock return Actually counted clock source
Counter value
N
N+1
N+2
N+3
N+4
N+5
N+6
Clock stopped
Figure 15.5 Example of Clock Control Operation
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Section 15 Asynchronous Event Counter (AEC)
15.5
Operating States of Asynchronous Event Counter
The operating states of the asynchronous event counter are shown in table 15.3. Table 15.3 Operating States of Asynchronous Event Counter
Operating Mode
AEGSR ECCR ECCSR ECH ECL IRQAEC
Reset Active
Reset Reset Reset Reset Reset Reset
Sleep
Watch
1
Sub-active Sub-sleep
Functioning Functioning Functioning
12 2
Standby
Retained* Retained* Retained*
2 1
Module Standby
Retained Retained Retained
12
Functioning Functioning Retained* Functioning Functioning Retained* Functioning Functioning Retained*
Functioning Functioning Functioning
1
1
1
1
Functioning Functioning Functioning* * Functioning* Functioning Functioning Functioning*1*2 Functioning2 Functioning Functioning Retained* Functioning Functioning Retained
3
Functioning* Functioning* * Halted Functioning*2 Functioning*1*2 Halted Functioning Retained Retained* Retained
3
Functioning Retained
Retained* Retained
4
Event counter Reset PWM
Notes: 1. When an asynchronous external event is input, the counter increments. In addition, when an overflow occurs, an interrupt is requested. 2. Functions when asynchronous external events are selected; halted and retained otherwise. 3. Clock control by IRQAEC operates, but interrupts do not. 4. As the clock is stopped in module standby mode, IRQAEC has no effect.
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Section 15 Asynchronous Event Counter (AEC)
15.6
Usage Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in 8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the counter. The correct value will not be returned if the event counter increments while being read. 2. For input to the AEVH and AEVL pins, use a clock with a frequency of up to 4.2 MHz within the range from 1.8 to 3.6 V and up to 10 MHz within the range from 2.7 to 3.6 V. For the high and low widths of the clock, see section 26, Electrical Characteristics. The duty cycle is arbitrary. Table 15.4 shows a maximum clock frequency. Table 15.4 Maximum Clock Frequency
Mode Active (high-speed), sleep (high-speed) Active (medium-speed), sleep (medium-speed) (OSC/8) Maximum Clock Frequency Input to AEVH/AEVL Pin 10 MHz 2 fOSC (OSC/16) fOSC (OSC/32) 1/2 fOSC fOSC = 2 MHz to 4 MHz Watch, subactive, subsleep, standby W = 32.768 kHz or 38.4 kHz (OSC/64) 1/4 fOSC (W/2) (W/4) (W/8) 1000 kHz 500 kHz 250 kHz
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1 second, or set both CUEH and CRCH to 1 at same time before clock input. When AEC is operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up. 4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR and ECPWDR should not be modified. When changing the data, clear the ECPWME bit in AEGSR to 0 (halt the event counter PWM) before modifying these registers. 5. The event counter PWM data register and event counter PWM compare register must be set so that event counter PWM data register < event counter PWM compare register. If the settings do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
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Section 15 Asynchronous Event Counter (AEC)
6. As synchronization is established internally when an IRQAEC interrupt is generated, a maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
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Section 16 Watchdog Timer
Section 16 Watchdog Timer
This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog timer function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.
16.1
Features
The WDT features are described below. * Selectable from eleven counter input clocks Ten internal clock sources (/64, /128, /256, /512, /1024, /2048, /4096, /8192, W/16, and W/256) or the on-chip watchdog timer oscillator can be selected as the timer-counter clock. * Watchdog timer mode If the counter overflows, this LSI is internally reset. * Interval timer mode If the counter overflows, an interval timer interrupt is generated. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (The WDT is operating as the initial value. For details, refer to section 6.4, Module Standby Function.)
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Section 16 Watchdog Timer
Figure 16.1 shows a block diagram of the WDT.
TMWD
PSS
TCWD
[w/16 or w/256]
TCSRWD2
Internal data bus
Interrupt/reset control Internal reset signal or interrupt request signal
On-chip WDT oscillator
TCSRWD1
[Legend] TCSRWD1: TCSRWD2: TCWD: TMWD: PSS: Timer control/status register WD1 Timer control/status register WD2 Timer counter WD Timer mode register WD Prescaler S
Figure 16.1 Block Diagram of Watchdog Timer
16.2
Register Descriptions
The watchdog timer has the following registers. * Timer control/status register WD1 (TCSRWD1) * Timer control/status register WD2 (TCSRWD2) * Timer counter WD (TCWD) * Timer mode register WD (TMWD)
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Section 16 Watchdog Timer
16.2.1
Timer Control/Status Register WD1 (TCSRWD1)
TCSRWD1 performs the TCSRWD1 and TCWD write control. TCSRWD1 also controls the watchdog timer operation and indicates the operating state. TCSRWD1 must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit 7 Bit Name B6WI Initial Value 1 R/W R/W Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0. This bit is always read as 1. 6 TCWE 0 R/W Timer Counter WD Write Enable TCWD can be written when the TCWE bit is set to 1. When writing data to this bit, the write value for bit 7 must be 0. 5 B4WI 1 R/W Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1. 4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the write value for bit 5 must be 0. 3 B2WI 1 R/W Bit 2 Write Inhibit The WDON bit can be written only when the write value of the B2WI bit is 0. This bit is always read as 1.
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Section 16 Watchdog Timer
Bit 2
Bit Name WDON
Initial Value 1
R/W R/W
Description Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. [Setting condition] * * * When 1 is written to the WDON bit and 0 to the B2WI bit while the TCSRWE bit is 1 Reset by RES pin When 0 is written to the WDON bit and 0 to the B2WI bit while the TCSRWE bit is 1
[Clearing condition]
1
B0WI
1
R/W
Bit 0 Write Inhibit The WRST bit can be written only when the write value of the B0WI bit is 0. This bit is always read as 1.
0
WRST
0
R/W
Watchdog Timer Reset Indicates whether a reset caused by the watchdog timer is generated. This bit is not cleared by a reset caused by the watchdog timer. [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing conditions] * * Reset by RES pin When 0 is written to the WRST bit and 0 to the B0WI bit while the TCSRWE bit is 1
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Section 16 Watchdog Timer
16.2.2
Timer Control/Status Register WD2 (TCSRWD2)
TCSRWD2 performs the TCSRWD2 write control, mode switching, and interrupt control. TCSRWD2 must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit 7 Bit Name OVF Initial Value 0 R/W
1
Description
R/(W)* Overflow Flag Indicates that TCWD has overflowed (changes from H'FF to H'00). [Setting condition] TCWD overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, this bit is cleared automatically by the internal reset after it has been set. [Clearing condition] * TCSRWD2 is read when OVF = 1, then 0 is written to OVF
6
B5WI
1
R/(W)* Bit 5 Write Inhibit The WT/IT bit can be written only when the write value of the B5WI bit is 0. This bit is always read as 1.
2
5
WT/IT
0
R/(W)* Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Watchdog timer mode 1: Interval timer mode
3
4
B3WI
1
R/(W)* Bit 3 Write Inhibit The IEOVF bit can be written only when the write value of the B3WI bit is 0. This bit is always read as 1.
2
3
IEOVF
0
R/(W)* Overflow Interrupt Enable Enables or disables an overflow interrupt request in interval timer mode. 0: Disables an overflow interrupt 1: Enables an overflow interrupt
3
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Section 16 Watchdog Timer
Bit 2 to 0
Bit Name
Initial Value All 1
R/W
Description Reserved These bits are always read as 1.
Notes: 1. Only 0 can be written to clear the flag. 2. Write operation is necessary because this bit controls data writing to other bit. This bit is always read as 1. 3. Writing is possible only when the write conditions are satisfied.
16.2.3
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD1 is set to 1. TCWD is initialized to H'00.
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Section 16 Watchdog Timer
16.2.4
Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit 7 to 4 3 2 1 0 Bit Name CKS3 CKS2 CKS1 CKS0 Initial Value All 1 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1. Clock Select 3 to 0 Select the clock to be input to TCWD. 00xx: On-chip WDT oscillator 0100: Internal clock: counts on W/16 0101: Internal clock: counts on W/256 011x: Reserved 1000: Internal clock: counts on /64 1001: Internal clock: counts on /128 1010: Internal clock: counts on /256 1011: Internal clock: counts on /512 1100: Internal clock: counts on /1024 1101: Internal clock: counts on /2048 1110: Internal clock: counts on /4096 1111: Internal clock: counts on /8192 For the overflow periods of the on-chip WDT oscillator, see section 26, Electrical Characteristics. In active (medium-speed), sleep (medium-speed), subactive, and subsleep modes, the 00xx value and the interval timer mode cannot be set simultaneously. In subactive and subsleep modes, when the subclock frequency is W/8, the 010x value and the interval timer mode cannot be set simultaneously. [Legend] x: Don't care
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Section 16 Watchdog Timer
16.3
16.3.1
Operation
Watchdog Timer Mode
The watchdog timer is provided with an 8-bit up-counter. To use it as the watchdog timer, clear the WT/IT bit in TCSRWD2 to 0. (To write the WT/IT bit, two write accesses are required.) If 1 is written to the WDON bit and 0 to the B2WI bit simultaneously when the TCSRWE bit in TCSRWD1 is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD1 are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 512 clock cycles of the on-chip watchdog timer oscillator. TCWD is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. Figure 16.2 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when = 4 MHz 4 x 106 8192 x 30 x 10-3 = 14.6
Therefore, 256 - 15 = 241 (H'F1) is set in TCWD. TCWD overflow
H'FF H'F1 TCWD count value
H'00 Start H'F1 written to TCWD Internal reset signal 512 clock cycles (on-chip WDT oscillator) H'F1 written to TCWD Reset generated
Figure 16.2 Example of Watchdog Timer Operation
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Section 16 Watchdog Timer
16.3.2
Interval Timer Mode
Figure 16.3 shows the operation in interval timer mode. To use the WDT as an interval timer, set the WT/IT bit in TCSRWD2 to 1. When the WDT is used as an interval timer, an interval timer interrupt request is generated each time the TCWD overflows. Therefore, an interval timer interrupt can be generated at intervals.
H'FF
TCWD count value Time H'00 WT/IT = 1 Interval timer Interval timer Interval timer Interval timer Interval timer interrupt interrupt interrupt interrupt interrupt request generated request generated request generated request generated request generated
Figure 16.3 Interval Timer Mode Operation 16.3.3 Timing of Overflow Flag (OVF) Setting
Figure 16.4 shows the timing of the OVF flag setting. The OVF flag in TCSRWD2 is set to 1 if TCWD overflows. At the same time, a reset signal is output in watchdog timer mode and an interval timer interrupt is generated in interval timer mode.
TCWD H'FF H'00
Overflow signal
OVF
Figure 16.4 Timing of OVF Flag Setting
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Section 16 Watchdog Timer
16.4
Interrupt
During interval timer mode operation, an overflow generates an interval timer interrupt. The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSRWD2. The OVF flag must be cleared to 0 in the interrupt handling routine.
16.5
16.5.1
Usage Notes
Switching between Watchdog Timer Mode and Interval Timer Mode
If modes are switched between watchdog timer and interval timer, while the WDT is operating, an error may occur in the count value. Software must stop the watchdog timer (by clearing the WDON bit to 0) before switching modes. 16.5.2 Module Standby Mode Control
The WDCKSTP bit in CKSTPR2 is valid when the WDON bit in the timer control/status register WD1 (TCSRWD1) is cleared to 0. The WDCKSTP bit can be cleared to 0 while the WDON bit is set to 1 (while the watchdog timer is operating). However, the watchdog timer does not enter module standby mode but continues operating. When the WDON bit is cleared to 0 by software after the watchdog timer stops operating, the WDCKSTP bit is valid at the same time and the watchdog timer enters module standby mode. 16.5.3 Writing to Timer Counter WD (TCWD) with the On-Chip Watchdog Timer Oscillator Selected When the timer counter WD (TCWD) is written to with the on-chip watchdog timer oscillator selected as the clock to drive the counter, updating of values read from TCWD requires up to (onchip watchdog timer oscillator overflow time)/256. The watchdog timer does not overflow between writing of the new value to the register and updating of the read values.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Section 17 Serial Communications Interface 3 (SCI3, IrDA)
The serial communications interface 3 (SCI3) can handle both asynchronous and clock synchronous serial communications. The asynchronous method allows the handling of serial data communications with standard asynchronous communications chips such as Universal Asynchronous Receiver/Transmitters (UARTs) and Asynchronous Communications Interface Adapters (ACIAs). A function is also provided for serial communications between processors (multiprocessor communication function) on three channels (SCI3_1, SCI3_2, and SCI3_3). Table 17.1 shows the configuration of the SCI3 channels. The SCI3_1 can transmit and receive IrDA signals that conform to version 1.0 of the Infrared Data Association (IrDA) standard.
17.1
Features
* Choice of asynchronous or clock synchronous serial communications mode * Full-duplex communications capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * On-chip baud rate generator, internal clock, or external clock can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. * Use of module standby mode enables this module to be placed in standby mode independently when it is not in use (for details, see section 6.4, Module Standby Function). Asynchronous mode * Data length: 7, 8, or 5 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the RXD31, RXD32, or RXD33 pin level directly in the case of a framing error
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Clock synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Note: When using this function, do not use the on-chip oscillator for the system clock.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.1 SCI3 Channel Configuration
Channel Channel 1 Abbreviation SCI3_1 Pin*
1
Register* SMR3_1 BRR3_1 SCR3_1 TDR3_1 SSR3_1 RDR3_1 RSR3_1 TSR3_1 SEMR IrCR
2
Register Address H'FFFF98 H'FFFF99 H'FFFF9A H'FFFF9B H'FFFF9C H'FFFF9D H'FFFFA6 H'FFFFA7 H'FFFFA8 H'FFFFA9 H'FFFFAA H'FFFFAB H'FFFFAC H'FFFFAD H'FFF088 H'FFF089 H'FFF08A H'FFF08B H'FFF08C H'FFF08D
SCK31 RXD31 TXD31
Channel 2
SCI3_2
SCK32 RXD32 TXD32
SMR3_2 BRR3_2 SCR3_2 TDR3_2 SSR3_2 RDR3_2 RSR3_2 TSR3_2
Channel 3
SCI3_3
SCK33 RXD33 TXD33
SMR3_3 BRR3_3 SCR3_3 TDR3_3 SSR3_3 RDR3_3 RSR3_3 TSR3_3
Notes: 1. Pin names SCK3, RXD3, and TXD3 are used in the text for all channels, omitting the channel designation. 2. In the text, channel description is omitted for registers and bits.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Figures 17.1 (1), 17.1 (2), and 17.1 (3) show block diagrams of the SCI3_1, SCI3_2, and SCI3_3, respectively.
SCK31
External clock Baud rate generator
Internal clock (/64, /16, w/2, )
BRC3_1
BRR3_1
Clock
SEMR SMR3_1 Transmit/receive control circuit SCR3_1 SSR3_1 TSR3_1 TDR3_1
RSR3_1 TXD31 RXD31 SPCR IrCR
RDR3_1
Interrupt request (TEI31, TXI31, RXI31, ERI31)
[Legend] RSR3_1: Receive shift register 3_1 RDR3_1:Receive data register 3_1 TSR3_1: Transmit shift register 3_1 TDR3_1: Transmit data register 3_1 SMR3_1:Serial mode register 3_1 SCR3_1: Serial control register 3_1 SSR3_1: Serial status register 3_1 BRR3_1: Bit rate register 3_1 BRC3_1: Bit rate counter 3_1 SPCR: Serial port control register IrDA control register IrCR: SEMR: Serial extended mode register
Figure 17.1 (1) Block Diagram of SCI3_1
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Internal data bus
Section 17 Serial Communications Interface 3 (SCI3, IrDA)
SCK32
External clock Baud rate generator
Internal clock (/64, /16, w/2, )
BRC3_2 Clock
BRR3_2
Transmit/receive control circuit
SCR3_2 SSR3_2
TXD32
TSR3_2
TDR3_2
RXD32 SPCR
RSR3_2
RDR3_2
Interrupt request (TEI32, TXI32, RXI32, ERI32) [Legend] RSR3_2: RDR3_2: TSR3_2: TDR3_2: SMR3_2: SCR3_2: SSR3_2: BRR3_2: BRC3_2: SPCR:
Receive shift register 3_2 Receive data register 3_2 Transmit shift register 3_2 Transmit data register 3_2 Serial mode register 3_2 Serial control register 3_2 Serial status register 3_2 Bit rate register 3_2 Bit rate counter 3_2 Serial port control register
Figure 17.1 (2) Block Diagram of SCI3_2
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Internal data bus
SMR3_2
Section 17 Serial Communications Interface 3 (SCI3, IrDA)
SCK33
External clock Baud rate generator
Internal clock (/64, /16, w/2, )
BRC3_3 Clock
BRR3_3
Transmit/receive control circuit
SCR3_3 SSR3_3
TXD33
TSR3_3
TDR3_3
RXD33 SPCR2
RSR3_3
RDR3_3
Interrupt request (TEI33, TXI33, RXI33, ERI33) [Legend] RSR3_3: RDR3_3: TSR3_3: TDR3_3: SMR3_3: SCR3_3: SSR3_3: BRR3_3: BRC3_3: SPCR2:
Receive shift register 3_3 Receive data register 3_3 Transmit shift register 3_3 Transmit data register 3_3 Serial mode register 3_3 Serial control register 3_3 Serial status register 3_3 Bit rate register 3_3 Bit rate counter 3_3 Serial port control register 2
Figure 17.1 (3) Block Diagram of SCI3_3
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Internal data bus
SMR3_3
Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.2
Input/Output Pins
Table 17.2 shows the SCI3 pin configuration. Table 17.2 Pin Configuration
Pin Name SCI3 clock Abbreviation I/O SCK31, SCK32, SCK33 RXD31, RXD32, RXD33 TXD31, TXD32, TXD33 I/O Function SCI3 clock input/output
SCI3 receive data input SCI3 transmit data output
Input
SCI3 receive data input
Output
SCI3 transmit data output
17.3
Register Descriptions
The SCI3 has the following registers for each channel. * Receive shift register 3 (RSR3)* * Receive data register 3 (RDR3)* * Transmit shift register 3 (TSR3)* * Transmit data register 3 (TDR3)* * Serial mode register 3 (SMR3)* * Serial control register 3 (SCR3)* * Serial status register 3 (SSR3)* * Bit rate register 3 (BRR3)* * Serial port control register (SPCR) * Serial port control register 2 (SPCR2) * IrDA control register (IrCR) * Serial extended mode register (SEMR) Note: * These register names are abbreviated to RSR, RDR, TSR, TDR, SMR, SCR, SSR, and BRR in the text.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.3.1
Receive Shift Register (RSR)
RSR is a shift register that receives serial data input from the RXD3 pin and converts it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 17.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI3 has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. RDR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode. 17.3.3 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, and then sends the data that starts from the LSB to the TXD3 pin. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if the TDRE bit in SSR is set to 1). TSR cannot be directly accessed by the CPU. 17.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. TDR is initialized to H'FF by a reset or in standby mode, watch mode, or module standby mode.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.3.5
Serial Mode Register (SMR)
SMR sets the SCI3's serial communication format and selects the clock source for the on-chip baud rate generator. SMR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit 7 Bit Name COM Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 or 5 bits as the data length 1: Selects 7 or 5 bits as the data length When 7-bit data is selected. the MSB (bit 7) in TDR is not transmitted. To select 5 bits as the data length, set 1 to both the PE and MP bits. The three most significant bits (bits 7, 6, and 5) in TDR are not transmitted. In clock synchronous mode, the data length is fixed to 8 bits regardless of the CHR bit setting. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. In clock synchronous mode, parity bit addition and checking is not performed regardless of the PE bit setting.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Bit 4
Bit Name PM
Initial Value 0
R/W R/W
Description Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number, in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number, in reception, a check is carried out to confirm that the number of 1bits in the receive data plus the parity bit is an odd number. If parity bit addition and checking is disabled in clock synchronous mode and asynchronous mode, the PM bit setting is invalid.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
2
MP
0
R/W
Multiprocessor Mode When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and PM bit settings are invalid. In clock synchronous mode, this bit should be cleared to 0.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Bit 1 0
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W R/W
Description Clock Select 0 and 1 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: W/2 clock (n = 0) 10: /16 clock (n = 2) 11: /64 clock (n = 3) When W/2 clock is selected in subactive mode and subsleep mode, the SCI3 is only enabled when W/2 clock is selected for the CPU operating clock. For the relationship between the bit rate register setting and the baud rate, see section 17.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 17.3.8, Bit Rate Register (BRR)).
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.3.6
Serial Control Register (SCR)
SCR enables or disables SCI3 transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, refer to section 17.8, Interrupt Requests. SCR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI3 interrupt request is enabled. TXI3 can be released by clearing the TDRE bit or TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI3 and ERI3 interrupt requests are enabled. RXI3 and ERI3 can be released by clearing the RDRF bit or the FER, PER, or OER error flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. When this bit is 0, the TDRE bit in SSR is fixed at 1. When transmit data is written to TDR while this bit is 1, Bit TDRE in SSR is cleared to 0 and serial data transmission is started. Be sure to carry out SMR settings, and setting of bit SPC3 in SPCR or SPCR2, to decide the transmission format before setting bit TE to 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in clock synchronous mode. Be sure to carry out the SMR settings to decide the reception format before setting bit RE to 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Bit 3
Bit Name MPIE
Initial Value 0
R/W R/W
Description Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 17.6, Multiprocessor Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable When this bit is set to 1, the TEI3 interrupt request is enabled. TEI3 can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0.
1 0
CKE1 CKE0
0 0
R/W R/W
Clock Enable 0 and 1 Select the clock source. Asynchronous mode: 00: Internal baud rate generator (The SCK3 pin functions as an I/O port) 01: Internal baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK3 pin) 10: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin) 11: Reserved Clock synchronous mode: 00: Internal clock (The SCK3 pin functions as clock output) 01: Reserved 10: External clock (The SCK3 pin functions as clock input) 11: Reserved
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.3.7
Serial Status Register (SSR)
SSR consists of status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. SSR is initialized to H'84 by a reset or in standby mode, watch mode, or module standby mode.
Bit 7 Bit Name TDRE Initial Value 1 R/W Description
R/(W)* Transmit Data Register Empty Indicates that transmit data is stored in TDR. [Setting conditions] * * * * The TE bit in SCR is 0 Data is transferred from TDR to TSR Writing of 0 to bit TDRE after reading TDRE = 1 The transmit data is written to TDR
[Clearing conditions]
6
RDRF
0
R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * Serial reception ends normally and receive data is transferred from RSR to RDR Writing of 0 to bit RDRF after reading RDRF = 1
[Clearing condition] * When data is read from RDR If an error is detected in reception, or if the RE bit in SCR has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will occur and the receive data will be lost.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Bit 5
Bit Name OER
Initial Value 0
R/W
Description
R/(W)* Overrun Error [Setting condition] * * An overrun error occurs in reception Writing of 0 to bit OER after reading OER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit OER is not affected and retains its previous state. When an overrun error occurs, RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in clock synchronous mode, transmission cannot be continued either.
4
FER
0
R/(W)* Framing Error [Setting condition] * * A framing error occurs in reception Writing of 0 to bit FER after reading FER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit FER is not affected and retains its previous state. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs, the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In clock synchronous mode, neither transmission nor reception is possible when bit FER is set to 1.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Bit 3
Bit Name PER
Initial Value 0
R/W
Description
R/(W)* Parity Error [Setting condition] * * A parity error is generated during reception Writing of 0 to bit PER after reading PER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit PER is not affected and retains its previous state. Receive data in which a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In clock synchronous mode, neither transmission nor reception is possible when bit PER is set to 1.
2
TEND
1
R
Transmit End [Setting conditions] * * The TE bit in SCR is 0 TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Writing of 0 to bit TDRE after reading TDRE = 1 The transmit data is written to TDR
[Clearing conditions] * * 1 MPBR 0 R
Multiprocessor Bit Receive MPBR stores the multiprocessor bit in the receive character data. When the RE bit in SCR is cleared to 0, its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit character data.
Note:
*
Only 0 can be written to clear the flag.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.3.8
Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that specifies the bit rate. BRR is initialized to H'FF. Tables 17.3 and 17.4 show examples of the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in asynchronous mode. Table 17.6 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in these tables are values in active (high-speed) mode. When the ABCS bit in SEMR is set to 1 in asynchronous mode, the maximum bit rate is twice the values shown in table 17.6. Tables 17.7 (1) and (2) show examples of the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in clock synchronous mode. The values shown in these tables are values in active (high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode, ABCS = 0]
N= -1 32 x 22n x B
B (bit rate obtained from n, N, ) - R (bit rate in left-hand column in table 17.3) R (bit rate in left-hand column in table 17.3) x 100
Error (%) =
[Asynchronous Mode, ABCS = 1*]
N= -1 16 x 22n x B
B (bit rate obtained from n, N, ) - R (bit rate in left-hand column in table 17.4) R (bit rate in left-hand column in table 17.4) x 100
Error (%) =
[Legend] B: N: : n: Note: *
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The correspondence between n and the clock is shown in table 17.5) Only supported by the SCI3_1 interface.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (1)
Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 32.8 kHz n -- -- -- 0 -- -- -- -- -- -- -- -- -- N -- -- -- 1 -- -- -- -- -- -- -- -- -- Error (%) -- -- -- 2.50 -- -- -- -- -- -- -- -- -- n -- 0 0 -- 0 0 -- -- -- -- -- -- -- 38.4 kHz N -- 3 2 -- 1 0 -- -- -- -- -- -- -- Error (%) -- 0.00 0.00 -- 0.00 0.00 -- -- -- -- -- -- -- n 2 2 2 0 0 0 0 0 0 -- -- 0 -- 2 MHz N 35 25 19 249 207 103 51 25 12 -- -- 1 -- Error (%) -1.36 0.16 -2.34 0.00 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- n 2 2 2 2 0 0 0 0 0 0 -- -- -- 2.097152 MHz N 36 26 19 15 217 108 54 26 13 6 -- -- -- Error (%) 0.64 1.14 2.40 2.40 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- --
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (2)
Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 2.4576 MHz n 2 2 2 2 0 0 0 0 0 0 0 -- 0 N 43 31 23 18 255 127 63 31 15 7 3 -- 1 Error (%) -0.83 0.00 0.00 1.05 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 2 0 0 0 0 0 0 0 -- 3 MHz N 52 38 28 22 19 155 77 38 19 9 4 2 -- Error (%) 0.50 0.16 1.02 1.90 -2.34 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- n 2 2 2 2 2 0 0 0 0 0 0 -- 0 3.6864 MHz N 64 47 35 28 23 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 -0.69 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 2 0 0 0 0 0 -- 0 -- 4 MHz N 70 51 38 30 25 207 103 51 25 12 -- 3 -- Error (%) 0.03 0.16 0.16 0.81 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 --
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (3)
Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 4.194304 MHz n 2 2 2 2 2 0 0 0 0 0 0 -- -- N 73 54 40 32 26 217 108 54 26 13 6 -- -- Error (%) 0.64 -0.70 -0.10 -0.70 1.14 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- n 2 2 2 2 2 0 0 0 0 0 0 0 0 4.9152MHz N 86 63 47 37 31 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 1.05 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 2 2 2 0 0 0 0 0 0 0 5 MHz N 88 64 48 38 32 15 129 64 32 15 7 4 3 Error (%) -0.25 0.16 -0.35 0.16 -1.36 1.73 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 2 2 2 2 2 0 0 0 0 0 0 0 6 MHz N 106 77 58 46 38 19 155 77 38 19 9 5 4 Error (%) -0.44 0.16 -0.69 -0.27 0.16 -2.34 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 0) (4)
Bit Rate (bit/s) n 110 150 200 250 300 600 1200 2400 4800 9600 2 2 2 2 2 2 0 0 0 0 6.144 MHz N 108 79 59 47 39 19 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 2 2 2 0 0 0 0 0 -- 0 7.3728 MHz N 130 95 71 57 47 23 191 95 47 23 11 -- 5 Error (%) -0.07 0.00 0.00 -0.69 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 2 2 0 0 0 0 0 0 -- 8 MHz N 141 103 77 62 51 25 207 103 51 25 12 7 -- Error (%) 0.03 0.16 0.16 -0.79 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- n 2 2 2 2 2 2 0 0 0 0 0 0 0 9.8304 MHz N 174 127 95 76 63 31 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 2 2 2 2 0 0 0 0 0 0 10 MHz N 177 129 97 77 64 32 15 129 64 32 15 9 7 Error (%) -0.25 0.16 -0.35 0.16 0.16 -1.36 1.73 0.16 0.16 -1.36 1.73 0.00 1.73
19200 0 31250 0 38400 0
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (1)
Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 32.8 kHz n -- 0 0 0 -- -- -- -- -- -- -- -- -- N -- 6 4 3 -- -- -- -- -- -- -- -- -- Error (%) -- -2.38 2.50 2.50 -- -- -- -- -- -- -- -- -- n 0 0 0 -- 0 0 0 -- -- -- -- -- -- 38.4 kHz N 10 7 5 -- 3 1 0 -- -- -- -- -- -- Error (%) -0.83 0.00 0.00 -- 0.00 0.00 0.00 -- -- -- -- -- -- n 2 2 2 2 2 0 0 0 0 0 -- 0 -- 2 MHz N 70 51 38 30 25 Error (%) 0.03 0.16 0.16 0.81 0.16 n 2 2 2 2 2 0 0 0 0 0 0 -- -- 2.097152 MHz N 73 54 40 32 26 217 108 54 26 13 6 -- -- Error (%) 0.64 -0.70 -0.10 -0.70 1.14 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- --
207 0.16 103 0.16 51 25 12 -- 3 -- 0.16 0.16 0.16 -- 0.00 --
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (2)
Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 2.4576 MHz n 2 2 2 2 2 0 0 0 0 0 0 0 0 N 86 63 47 37 31 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 1.05 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 2 2 2 0 0 0 0 0 0 0 3 MHz N 106 77 58 46 38 19 155 77 38 19 9 5 4 Error (%) -0.44 0.16 -0.69 -0.27 0.16 -2.34 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 2 2 2 2 0 0 0 0 0 -- 0 3.6864 MHz N 130 95 71 57 47 23 191 95 47 23 11 -- 5 Error (%) -0. 07 0.00 0.00 -0.69 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 2 2 0 0 0 0 0 0 -- 4 MHz N 141 103 77 62 51 25 207 103 51 25 12 7 -- Error (%) 0.03 0.16 0.16 -0.79 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 --
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (3)
Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 4.194304 MHz n 2 2 2 2 2 2 0 0 0 0 0 -- 0 N 148 108 81 65 54 26 217 108 54 26 13 -- 6 Error (%) -0.04 0.21 -0.10 -0.70 -0.70 1.14 0.21 0.21 -0.70 1.14 -2.48 -- -2.48 n 2 2 2 2 2 2 0 0 0 0 0 0 0 4.9152MHz N 174 127 95 76 63 31 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 2 2 2 2 0 0 0 0 0 0 5 MHz N 177 129 97 77 64 32 15 129 64 32 15 9 7 Error (%) -0.25 0.16 -0.35 0.16 0.16 -1.36 1.73 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 2 2 2 2 0 0 0 0 0 0 6 MHz N 212 155 116 93 77 38 19 155 77 38 19 11 9 Error (%) 0.03 0.16 0.16 -0.27 0.16 0.16 -2.34 0.16 0.16 0.16 -2.34 0.00 -2.34
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode, ABCS = 1) (4)
Bit Rate (bit/s) n 110 150 200 250 300 600 1200 2400 4800 9600 2 2 2 2 2 2 2 0 0 0 6.144 MHz N 217 159 119 95 79 39 19 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 3 2 2 2 2 2 2 0 0 0 0 0 0 7.3728 MHz N 64 191 143 114 95 47 23 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.17 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 2 2 2 2 0 0 0 0 0 0 8 MHz N 70 207 155 124 103 51 25 207 103 51 25 15 12 Error (%) 0.03 0.16 0.16 0.00 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 2 2 2 2 0 0 0 0 0 0 9.8304 MHz N 86 255 191 153 127 63 31 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 2 2 2 2 0 0 0 0 0 10 MHz N 88 64 194 155 129 64 32 15 129 64 32 19 15 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.16 0.16 -1.36 0.00 1.73
19200 0 31250 0 38400 0
Table 17.5 Correspondence between n and Clock
SMR Setting n 0 0 2 3 Note: Clock W/2* /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1
In subactive or subsleep mode, the SCI3_1, SCI3_2, and SCI3_3 interfaces can operate only when the CPU clock is W/2.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.6 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Rate (bit/s) (MHz) 0.0328* 0.0384* 2 2.097152 2.4576 3 3.6864 4 4.194304 4.9152 5 6 6.144 7.3728 8 9.8304 10 Note:
1 1
Setting n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ABCS = 0 512 600 62500 65536 76800 93750 115200 125000 131072 153600 156250 187500 192000 230400 250000 307200 312500
ABCS = 1* 1025 1200 125000 131072 153600 187500 230400 250000 262144 307200 312500 375000 384000 460800 500000 614400 625000
2
1. When CKS1 = 0 and CKS0 = 1 in SMR 2. Only supported by the SCI3_1 interface.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.7 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1)
Bit Rate (bit/s) 200 250 300 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M Note: * n 0 0 0 0 0 32.8 kHz N 20 15 13 7 3 Error (%) -2.38 2.50 -2.38 2.50 2.50 n 0 0 0 N 23 18 15 38.4 kHz Error (%) 0.00 1.05 0.00 n 2 2 2 2 2 0 0 0 0 0 0 0 0* N 155 124 103 62 30 199 99 49 19 9 4 1 0* 2 MHz Error (%) 0.16 0.00 0.16 -0.79 0.81 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00*
Continuous transmission/reception is not possible.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.7 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2)
Bit Rate (bit/s) 200 250 300 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M Note: * n 3 2 2 2 2 2 0 0 0 0 0 0 0 0* N 77 4 MHz Error (%) 0.16 n 3 3 3 2 2 2 2 0 0 0 0 0 0 0 N 8 MHz Error (%) n 3 3 3 3 2 2 2 0 0 0 0 0 0 N 194 155 129 77 155 62 30 249 99 49 24 9 4 10 MHz Error (%) 0.16 0.16 0.16 0.16 0.16 -0.79 0.81 0.00 0.00 0.00 0.00 0.00 0.00
155 0.16 124 0.00 103 0.16 249 0.00 124 0.00 49 24 0.00 0.00
249 0.00 207 0.16 124 0.00 62 24 -0.79 0.00
199 0.00 99 39 19 9 3 1 0* 0.00 0.00 0.00 0.00 0.00 0.00 0.00*
199 0.00 79 39 19 7 3 1 0.00 0.00 0.00 0.00 0.00 0.00
Continuous transmission/reception is not possible.
[Clock Synchronous Mode]
N= -1 4 x 22n x B
[Legend] B: N: : n:
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The correspondence between n and the clock is shown in table 17.8.)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.8 Correspondence between n and Clock
SMR Setting n 0 0 2 3 Clock W/2* /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1
Note: In subactive or subsleep mode, the SCI3_1, SCI3_2, and SCI3_3 interfaces can operate only when the CPU clock is W/2.
17.3.9
Serial Port Control Register (SPCR)
SPCR selects the functions of the TXD32 and TXD31/IrTXD pins, selects whether input data of the RXD32 pin and RXD31/IrRXD pin is inverted or not, and selects output data of the TXD32 pin and TXD31/IrTXD pin is inverted or not.
Bit 7 6 5 Bit Name SPC32 Initial Value 1 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. P32/TXD32/SCL (PE5/TXD32) Pin Function Switch Selects whether pin P32/TXD32/SCL (PE5/TXD32) is used as P32/SCL (PE5) or as TXD32. 0: P32/SCL (PE5) I/O pin 1: TXD32 output pin Set the TE bit in SCR3_2 after having set this bit to 1. 4 SPC31 0 R/W P42/TXD31/IrTXD/TMOFH (PF3/TXD31/IrTXD) Pin Function Switch Selects whether pin P42/TXD31/IrTXD/TMOFH (PF3/TXD31/IrTXD) is used as P42/TMOFH (PF3) or as TXD31/IrTXD. 0: P42 (PF3) I/O pin or TMOFH output pin 1: TXD31/IrTXD output pin Set the TE bit in SCR3_1 after having set this bit to 1.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Bit 3
Bit Name SCINV3
Initial Value 0
R/W R/W
Description TXD32 Pin Output Data Inversion Switch Selects whether the logic level of output data of the TXD32 pin is inverted or not. 0: TXD32 output data is not inverted. 1: TXD32 output data is inverted.
2
SCINV2
0
R/W
RXD32 Pin Input Data Inversion Switch Selects whether the logic level of input data of the RXD32 pin is inverted or not. 0: RXD32 input data is not inverted. 1: RXD32 input data is inverted.
1
SCINV1
0
R/W
TXD31/IrTXD Pin Output Data Inversion Switch Selects whether the logic level of output data of the TXD31/IrTXD pin is inverted or not. 0: TXD31/IrTXD output data is not inverted. 1: TXD31/IrTXD output data is inverted.
0
SCINV0
0
R/W
RXD31/IrRXD Pin Input Data Inversion Switch Selects whether the logic level of input data of the RXD31/IrRXD pin is inverted or not. 0: RXD31/IrRXD input data is not inverted. 1: RXD31/IrRXD input data is inverted.
Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.3.10 Serial Port Control Register 2 (SPCR2) SPCR2 selects the function of the TXD33 pin and selects whether or not data input on the RXD33 pin and output via the TXD33 pin are inverted.
Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 SPC33 0 R/W PE2/TXD33 Pin Function Switch Selects whether pin PE2/TXD33 is used as PE2 or as TXD33. 0: PE2 I/O pin 1: TXD33 output pin Set the TE bit in SCR3_3 after having set this bit to 1. 3 2 1 SCINV5 1 1 0 R/W Reserved These bits are always read as 1 and cannot be modified. TXD33 Pin Output Data Inversion Switch Specifies whether the logic level of output data of the TXD33 pin is inverted. 0: TXD33 output data is not inverted 1: TXD33 output data is inverted 0 SCINV4 0 R/W RXD33 Pin Input Data Inversion Switch Specifies whether the logic level of input data of the RXD33 pin is inverted. 0: RXD33 input data is not inverted 1: RXD33 input data is inverted Note: When the values in bits 1 and 0 of serial port control register 2 are changed, the data being input or output up to that point is inverted immediately after the change, and this may lead to the input or output of invalid data. Values in this control register must only be changed while changes to the data have no effect.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.3.11 IrDA Control Register (IrCR) IrCR controls the IrDA operation of the SCI3_1.
Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Selects whether the SCI3_1 I/O pins function as the SCI or IrDA. 0: TXD31/IrTXD or RXD31/IrRXD pin functions as TXD31 or RXD31 1: TXD31/IrTXD or RXD31/IrRXD pin functions as IrTXD or IrRXD 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select If the IrDA function is enabled, these bits set the highpulse width when encoding the IrTXD output pulse. 000: Bit rate x 3/16 001: /2 010: /4 011: /8 100: /16 101: Setting prohibited 11x: Setting prohibited 3 to 0 All 0 Reserved These bits are always read as 0 and cannot be modified. [Legend] x: Don't care
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.3.12 Serial Extended Mode Register (SEMR) SEMR controls extended functions of the SCI3_1, i.e. specifies the basic clock in asynchronous mode.
Bit 7 to 4 3 Bit Name ABCS Initial Value All 0 0 R/W R/W Description Reserved The write value should always be 0. Asynchronous Mode Basic Clock Select Selects the basic clock for one-bit interval in asynchronous mode. The ABCS setting is enabled in asynchronous mode (COM = 0 in SMR3) 0: Basic clock with a frequency 16 times the transfer rate 1: Basic clock with a frequency 8 times the transfer rate Clear this bit to 0 when the IrDA function is enabled. 2 to 0 All 0 Reserved These bits are always read as 0 and cannot be modified.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.4
Operation in Asynchronous Mode
Figure 17.2 shows the general format for asynchronous serial communication. Each frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In reception in asynchronous mode, synchronization is with falling edges of the start bits. The data is sampled on the 8th pulse of a clock signal with a frequency 16 times the bit rate, so that the transferred data is latched at the center of each bit. When the ABCS bit in SEMR is set to 1, data is sampled on the 4th pulse of a clock with a frequency 8 times the bit rate*. Internally, the SCI3 has independent transmitter and receiver units, which enables full duplex operation. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. Table 17.9 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in SMR as shown in table 17.10. Note: Only supported by the SCI3_1 interface.
LSB Serial Start data bit Transmit/receive data MSB Parity bit Stop bit 1 Mark state
1 bit
5, 7, or 8 bits One unit of transfer data (character or frame)
1 bit, or none
1 or 2 bits
Figure 17.2 Data Format in Asynchronous Communication
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.4.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3's serial clock source, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock signal is input on the SCK3 pin, its frequency should be 16 times the bit rate (or 8 times the bit rate when the ABCS bit in SEMR is set to 1*). For details on selection of the clock source, see table 17.11. When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that rising edges of the clock signal are in the middle of each bit of the data to be transferred, as shown in figure 17.3. Note: * Only supported by the SCI3_1 interface.
Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (frame)
Figure 17.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.9 Data Transfer Formats (Asynchronous Mode)
SMR CHR 0 PE 0 MP 0 STOP 0 1
START
Serial Data Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10
STOP
11
12
8-bit data
0
0
0
1
START
8-bit data
STOP
STOP
0
0
1
0
START
8-bit data
MPB
STOP
0
0
1
1
START
8-bit data
MPB
STOP
STOP
0
1
0
0
START
8-bit data
P
STOP
0
1
0
1
START
8-bit data
P
STOP
STOP
0
1
1
0
START
5-bit data
STOP
0
1
1
1
START
5-bit data
STOP
STOP
1
0
0
0
START
7-bit data
STOP
1
0
0
1
START
7-bit data
STOP
STOP
1
0
1
0
START
7-bit data
MPB
STOP
1
0
1
1
START
7-bit data
MPB
STOP
STOP
1
1
0
0
START
7-bit data
P
STOP
1
1
0
1
START
7-bit data
P
STOP
STOP
1
1
1
0
START
5-bit data
P
STOP
1
1
1
1
START
5-bit data
P
STOP
STOP
[Legend] START: Start bit STOP: Stop bit Parity bit P: Multiprocessor bit MPB:
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.10 SMR Settings and Corresponding Data Transfer Formats
SMR Bit 7 COM 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 x x Clock synchronous mode 8-bit data No No 5-bit data No Yes 7-bit data Yes 5-bit data No 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Data Length 8-bit data Data Transfer Format Multiprocessor Parity Bit Bit No No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No
[Legend] x: Don't care
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Table 17.11 SMR and SCR Settings and Clock Source Selection
SMR Bit 7 COM 0 Bit 1 CKE1 0 SCR Bit 0 CKE0 0 Mode Asynchronous mode Transmit/Receive Clock Clock Source Internal SCK Pin Function I/O port pins (pins are not assigned to the SCK31 or SCK32 functions) Output for clock with same frequency as bit rate External Clock synchronous Internal mode External Input for clock with frequency 16 times bit rate* Output for serial clock Input for serial clock
1 1 1 0 1 0 1 1 Note: 1 0 1 0 0 0 1 1 1
Reserved (Do not specify these combinations)
The input clock may have a frequency 8 times the bit rate when the ABCS bit in SEMR is set to 1 (only supported for SCI3_1).
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.4.2
SCI3 Initialization
Follow the flowchart as shown in figure 17.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. When the external clock is used in clock synchronous mode, the clock must not be supplied during initialization.
[1] Start initialization Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clocked synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1. [2] [3] No 1-bit interval elapsed? Yes Set SPC3 bit in SPCR or SPCR2 to 1 Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits. End [4] [4] Set the data transfer format in SMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Setting bits TE and RE enables the TXD3 and RXD3 pins to be used. Also set the RIE, TIE, TEIE, and MPIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit.
Clear TE and RE bits in SCR to 0 [1] Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
[2]
Set value in BRR Wait
[3]
Figure 17.4 Sample SCI3 Initialization Flowchart
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.4.3
Data Transmission
Figure 17.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI3 interrupt request is generated. Continuous transmission is possible because the TXI3 interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. The SCI3 checks the TDRE flag at the timing for sending the stop bit. 4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 17.6 shows a sample flowchart for transmission in asynchronous mode.
Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1
TDRE TEND LSI TXI3 interrupt operation request generated User processing TDRE flag cleared to 0 Data written to TDR TXI3 interrupt request generated TEI3 interrupt request generated
Figure 17.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Start transmission Set SPC3 bit in SPCR or SPCR2 to 1
[1]
Read TDRE flag in SSR
No TDRE = 1 Yes Write transmit data to TDR
[2]
Yes Continue data transmission? No
Read TEND flag in SSR
[1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. (After the TE bit is set to 1, one frame of 1 is output, then transmission is possible.) [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [3] To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear the TE bit in SCR to 0.
No TEND = 1 Yes No Break output? Yes Clear PDR to 0 and set PCR to 1
[3]
Clear TE bit in SCR to 0
End
Figure 17.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.4.4
Serial Data Reception
Figure 17.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit. * Parity check The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR). * Stop bit check The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked. * Status check The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated. Receive data is not transferred to RDR. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE3 bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is generated. Continuous reception is possible because the RXI3 interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Start bit Serial data 1 0 D0 D1
Receive data D7 1 frame
Parity Stop Start bit bit bit 0/1 1 0 D0
Receive data D1 D7 1 frame
Parity Stop bit bit 0/1 0
Mark state (idle state) 1
RDRF FER LSI operation User processing RXI3 interrupt request generated RDRF cleared to 0 RDR data read 0 stop bit detected ERI3 request in response to framing error Framing error processing
Figure 17.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Table 17.12 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.8 shows a sample flowchart for serial data reception. Table 17.12 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception. However, note that if RDR is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, the RDRF flag will be cleared to 0.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Start reception
Read OER, PER, and FER flags in SSR
[1]
Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR No RDRF = 1 Yes [2]
Read receive data in RDR
[1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RXD3 pin.
Yes Continue data reception? (A) No Clear RE bit in SCR to 0 [3]
End
Figure 17.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
[4] Error processing
No OER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing
No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0
End
Figure 17.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.5
Operation in Clock Synchronous Mode
Figure 17.9 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clock synchronous mode, the SCI3 receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
8-bit * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care One unit of transfer data (character or frame) *
Figure 17.9 Data Format in Clock Synchronous Communications 17.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR. When the SCI3 is operated on an internal clock, the serial clock is output from the SCK3 pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 17.5.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 17.4.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.5.3
Serial Data Transmission
Figure 17.10 shows an example of SCI3 operation for transmission in clock synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI3 interrupt request is generated. 3. 8-bit data is sent from the TXD3 pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD3 pin. 4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7). 5. 6. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI3 is generated. The SCK3 pin is fixed high.
Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
7.
1 frame TDRE TEND TXI3 interrupt LSI operation request generated User processing TDRE flag cleared to 0 Data written to TDR TXI3 interrupt request generated
1 frame
TEI3 interrupt request generated
Figure 17.10 Example of SCI3 Operation in Transmission in Clock Synchronous Mode
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Figure 17.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.
Start transmission
Set SPC3 bit in SPCR or SPCR2 to 1
[1]
[1]
Read TDRE flag in SSR
No TDRE = 1 [2] Yes
Write transmit data to TDR
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When clock output is selected and data is written to TDR, clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
[2]
Continue data reception? No
Yes
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR to 0
End
Figure 17.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.5.4
Serial Data Reception (Clock Synchronous Mode)
Figure 17.12 shows an example of SCI3 operation for reception in clock synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. The SCI3 stores the received data in RSR. 3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is generated.
Serial clock
Serial data
Bit 7
Bit 0 1 frame
Bit 7
Bit 0
Bit 1 1 frame
Bit 6
Bit 7
RDRF
OER LSI operation User processing RXI3 interrupt request generated RDRF flag cleared to 0 RDR data read RXI3 interrupt request generated RDR data has not been read (RDRF = 1) ERI interrupt request generated by overrun error Overrun error processing
Figure 17.12 Example of SCI3 Reception Operation in Clock Synchronous Mode
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.13 shows a sample flowchart for serial data reception.
Start reception
[1]
Read OER flag in SSR
[1]
[2]
Yes OER = 1? [4] No Overrun error processing (Continued below) Read RDRF flag in SSR [2] [4] RDRF = 1? Yes Read receive data in RDR [3]
No
Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1.
Yes Data reception continued? No Clear RE bit in SCR to 0 [4] Start overrun error processing [3]
Overrun error processing Clear OER flag in SSR to 0
End
Figure 17.13 Sample Serial Reception Flowchart (Clock Synchronous Mode)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.5.5
Simultaneous Serial Data Transmission and Reception
Figure 17.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Start transmission/reception Set SPC3 bit in SPCR or SPCR2 to 1
No
No
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the [1] Read TDRE flag in SSR TDRE flag is automatically cleared to 0. [2] Read SSR and check that the RDRF TDRE = 1 flag is set to 1, then read the receive data in RDR. Yes When data is read from RDR, the RDRF flag is automatically cleared to Write transmit data to TDR 0. [3] To continue serial transmission/ reception, before the MSB (bit 7) of Read OER flag in SSR the current frame is received, finish reading the RDRF flag, reading RDR. Yes Also, before the MSB (bit 7) of the OER = 1 [4] current frame is transmitted, read 1 from the TDRE flag to confirm that Overrun error processing No writing is possible. Then write data to TDR. When data is written to TDR, the Read RDRF flag in SSR [2] TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to RDRF = 1 0. [4] If an overrun error occurs, read the Yes OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Read receive data in RDR Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 17.13.
[3]
[1]
Yes
Data transmission/reception continued? No Clear TE and RE bits in SCR to 0 End
Figure 17.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clock Synchronous Mode)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.6
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 17.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI3 uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04)
[Legend] MPB: Multiprocessor bit
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID
Figure 17.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.6.1
Multiprocessor Serial Data Transmission
Figure 17.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Start transmission
Set SPC3 bit in SPCR or SPCR2 to 1 [1] [1] Read TDRE flag in SSR Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To output a break in serial transmission, set the port PCR to 1, clear PDR to 0, then clear the TE bit in SCR to 0.
No TDRE = 1 [2] Yes
Set MPBT bit in SSR
[3] Write transmit data to TDR
Yes [2] Data transmission continued? No
Read TEND flag in SSR
No TEND = 1? Yes No [3] Break output? Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR to 0
End
Figure 17.16 Sample Multiprocessor Serial Transmission Flowchart
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.6.2
Multiprocessor Serial Data Reception
Figure 17.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI3 interrupt request is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure 17.18 shows an example of SCI3 operation for multiprocessor format reception.
Start reception [1] Set MPIE bit in SCR to 1 [2] Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs.
[1] Set the MPIE bit in SCR to 1.
[2] Read OER and FER flags in SSR
OER + FER = 1? Yes
[3]
Read RDRF flag in SSR
RDRF = 1? No
Yes Read receive data in RDR
This station's ID?
Yes
No
Read OER and FER flags in SSR
OER + FER = 1? Yes
[3] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again. When data is read from RDR, the RDRF flag is automatically cleared to 0. [4] Read SSR and check that the RDRF flag is set to 1, then read the data in RDR.
[4]
No Read RDRF flag in SSR RDRF = 1? No
Yes Read receive data in RDR
[5]
Data reception continued?
Receive error processing
Yes (A)
No Clear RE bit in SCR to 0
End Start receive error processing
OER = 1? No FER = 1? No Yes Yes
[5] If a receive error occurs, read the OER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RXD3 pin value.
Overrun error processing
Break?
No Framing error processing
Yes
Clear OER and FER flags in SSR to 0 End
(A)
Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Start bit Serial data 1 0 D0
Receive data (ID1) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data1) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing RXI3 interrupt request generated MPIE cleared to 0 RDRF flag cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again ID1
RXI3 interrupt request is not generated, and RDR retains its state
(a) When data does not match this receiver's ID
Start bit Serial data 1 0 D0
Receive data (ID2) D1 1 frame D7
MPB 1
Stop Start bit bit 1 0 D0
Receive data (Data2) D1 1 frame D7
MPB 0
Stop bit 1
Mark state (idle state) 1
MPIE
RDRF RDR value LSI operation User processing ID1 ID2 Data2
RXI3 interrupt request generated MPIE cleared to 0
RDRF flag cleared to 0 RDR data read
RXI3 interrupt RDRF flag cleared request to 0 generated When data is this station's ID, reception is continued RDR data read MPIE set to 1 again
(b) When data matches this receiver's ID
Figure 17.18 Example of SCI3 Operation in Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.7
IrDA Operation
IrDA operation can be used with the SCI3_1. Figure 17.19 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in IrCR, the TXD31 and RXD31 pins in the SCI3_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTXD and IrRXD pins). Connecting these pins to the infrared data transceiver/receiver achieves infrared data communication based on the system defined by the IrDA standard version 1.0. In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming.
IrDA TXD31/IrTXD RXD31/IrRXD Pulse encoder Pulse encoder TXD RXD SCI3_1
SPCR
IrCR
Figure 17.19 IrDA Block Diagram
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.7.1
Transmission
During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 17.20). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in IrCR. According to the standard, the high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) + 1.08 s at maximum. For example, when the frequency of system clock is 10 MHz, being equal to or greater than 1.41 s, the high-level pulse width at minimum can be specified as 1.6 s. For serial data of level 1, no pulses are output.
UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1
0
Transmission
Reception
IR frame Start bit 0 Bit cycle 1 0 1 0 Data Stop bit 1 1 0 1
0
Pulse width is 1.6 s to 3/16 bit cycle
Figure 17.20 IrDA Transmission and Reception
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.7.2
Reception
During reception, IR frames are converted to UART frames using the IrDA interface before inputting to the SCI3_1. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the minimum width allowed, the pulse is not recognized. 17.7.3 High-Level Pulse Width Selection
Table 17.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 17.13 IrCKS2 to IrCKS0 Bit Settings
Operating Frequency (MHz) 2 2.097152 2.4576 3 3.6864 4.9152 5 6 6.144 7.3728 8 9.8304 10 2400 78.13 010 010 010 011 011 011 011 100 100 100 100 100 100 Bit Rate (bps) (Upper Row) / Bit Interval x 3/16 (s) (Lower Row) 9600 19.53 010 010 010 011 011 011 011 100 100 100 100 100 100 19200 9.77 010 010 010 011 011 011 011 100 100 100 100 100 100 38400 4.88 010 010 010 011 011 011 011 100 100 100 100 100 100
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.8
Interrupt Requests
The SCI3 creates the following six interrupt requests: transmit end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 17.14 shows the interrupt sources. Table 17.14 SCI3 Interrupt Requests
Interrupt Requests Receive data full Transmit data empty Transmission end Receive error Abbreviation RXI3 TXI3 TEI3 ERI3 Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, and PER in SSR
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR. When the TDRE bit in SSR is set to 1, a TXI3 interrupt is requested. When the TEND bit in SSR is set to 1, a TEI3 interrupt is requested. These two interrupts are generated during transmission. The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR is set to 1 before transferring the transmit data to TDR, a TXI3 interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR is set to 1 before transferring the transmit data to TDR, a TEI3 interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI3 and TEI3), set the enable bits (TIE and TEIE) that correspond to these interrupt requests to 1, after transferring the transmit data to TDR. When the RDRF bit in SSR is set to 1, an RXI3 interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI3 interrupt is requested. These two interrupt requests are generated during reception. The SCI3 can carry out continuous reception using an RXI3 and continuous transmission using a TXI3.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
These interrupts are shown in table 17.15. Table 17.15 Transmit/Receive Interrupts
Interrupt RXI3 Flags RDRF RIE Interrupt Request Conditions When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, an RXI3 is enabled and an interrupt is requested. (See figure 17.21 (a).) When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, a TXI3 is enabled and an interrupt is requested. (See figure 17.21 (b).) When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, a TEI3 is enabled and an interrupt is requested. (See figure 17.21 (c).) Notes The RXI3 interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. The TXI3 interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. A TEI3 indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is transmitted.
TXI3
TDRE TIE
TEI3
TEND TEIE
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
RDR
RDR
RSR (reception in progress) RXD3 pin RXD3 pin
RSR (reception completed, transfer)
RDRF = 0
RDRF
(RXI3 request when RIE = 1)
Figure 17.21 (a) RDRF Setting and RXI3 Interrupt
TDR (next transmit data) TDR
TSR (transmission in progress) TXD3 pin TXD3 pin
TSR (transmission completed, transfer)
TDRE = 0
TDRE
1
(TXI3 request when TIE = 1)
Figure 17.21 (b) TDRE Setting and TXI3 Interrupt
TDR TDR
TSR (transmission in progress) TXD3 pin TXD3 pin
TSR (transmission completed)
TEND = 0
TEND
(TEI3 request when TEIE = 1)
Figure 17.21 (c) TEND Setting and TEI3 Interrupt
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1
1
Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.9
17.9.1
Usage Notes
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD3 pin value directly. In a break, the input from the RXD3 pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 17.9.2 Mark State and Break Sending
When TE is 0, the TXD3 pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TXD3 pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TXD3 pin becomes an I/O port, and 1 is output from the TXD3 pin. To send a break during serial transmission, first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TXD3 pin becomes an I/O port, and 0 is output from the TXD3 pin. 17.9.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.9.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate (8 times the transfer rate when the ABCS bit in SEMR is set to 1). In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock (4th pulse of the basic clock when the ABCS bit in SEMR is set to 1*) as shown in figure 17.22.The reception margin in asynchronous mode is given by formula (1) below. Note: Only supported by the SCI3_1 interface.
1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100(%) 2N N
... Formula (1)
Where N: D: L: F:
Ratio of bit rate to clock (N = 16) Clock duty (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula.
M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
16 clocks 8 clocks 0 Internal basic clock Receive data (RXD3) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 17.22 Receive Data Sampling Timing in Asynchronous Mode
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.9.5
Note on Switching SCK3 Pin Function
If pin SCK3 is used as a clock output pin by the SCI3 in clock synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock () cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. (1) When SCK3 Function is Switched from Clock Output to Non Clock-Output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents the SCK3 pin from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to the SCK3 pin, the line connected to the SCK3 pin should be pulled up to the VCC level via a resistor, or supplied with output from an external device. (2) When SCK3 Function is Switched from Clock Output to General Input/Output
When stopping data transfer, 1. Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1 and 0, respectively. 2. Clear bit COM in SMR to 0 3. Clear bits CKE1 and CKE0 in SCR to 0. Note that special care is also needed here to avoid an intermediate level of voltage from being applied to the SCK3 pin. 17.9.6 Relation between Writing to TDR and Bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not two or more times).
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.9.7
Relation between RDR Reading and bit RDRF
In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is shown in figure 17.23.
Frame 1 Communication line Data 1 Frame 2 Data 2 Frame 3 Data 3
RDRF
RDR
Data 1 (A)
RDR read
Data 2 (B)
RDR read
Data 1 is read at point (A) Data 2 is read at point (B)
Figure 17.23 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clock synchronous mode, or before the STOP bit is transferred in asynchronous mode.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
17.9.8
Transmit and Receive Operations when Making State Transition
Make sure that transmit and receive operations have completely finished before carrying out state transition processing. 17.9.9 Setting in Subactive or Subsleep Mode
In subactive or subsleep mode, the SCI3 interface can operate only when the CPU clock is W/2. The SA1 and SA0 bits in SYSCR2 should be set to 1 and 0, respectively. 17.9.10 Oscillator when Serial Communications Interface 3 is Used When the serial communications interface 3 is used, do not use the on-chip oscillator for the system clock. For details on selecting the system clock oscillator or on-chip oscillator for the system clock, see section 5.2.4, Selecting On-Chip Oscillator for System Clock.
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Section 17 Serial Communications Interface 3 (SCI3, IrDA)
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Section 18 Serial Communication Interface 4 (SCI4)
Section 18 Serial Communication Interface 4 (SCI4)
The serial communication interface 4 (SCI4) can handle clock synchronous serial communication with the 8-bit buffer. The SCI4 is supported only by the F-ZTAT version. When the on-chip emulator debugger etc. is used, the SCK4, SI4, and SO4 pins of the SCI4 are used by the system, and the SCI4 is not available for the user.
18.1
Features
* Eight internal clocks (/1024, /256, /64, /32, /16, /8, /4, /2) or external clock can be selected as a clock source. * Receive error detection: Overrun errors detected * Four interrupt sources Transmit-end, transmit-data-empty, receive-data-full, and overrun error * Full-duplex communication capability Buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * When the on-chip emulator debugger etc. is not used, the SCI4 is available for the user. * Use of module standby mode enables this module to be placed in standby mode independently when it is not in use. (For details, refer to section 6.4, Module Standby Function.)
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Section 18 Serial Communication Interface 4 (SCI4)
Figure 18.1 shows a block diagram of the SCI4.
PSS
SCK4 Transmit/receive control circuit
SCSR4 SCR4 TDR4
SI4 SO4
SR4
RDR4 TEI TXI RXI ERI
[Legend] SCSR4: Serial control status register 4 SCR4: Serial control register 4 TDR4: Transmit data register 4 SR4: Shift register 4 RDR4: Receive data register 4
Figure 18.1 Block Diagram of SCI4
18.2
Input/Output Pins
Table 18.1 shows the SCI4 pin configuration. Table 18.1 Pin Configuration
Pin Name SCI4 clock SCI4 data input SCI4 data output Abbreviation SCK4 SI4 SO4 I/O I/O Input Output Function SCI4 clock input/output SCI4 receive data input SCI4 transmit data output
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Internal data bus
Section 18 Serial Communication Interface 4 (SCI4)
18.3
Register Descriptions
The SCI4 has the following registers. * Serial control register 4 (SCR4) * Serial control/status register 4 (SCSR4) * Transmit data register 4 (TDR4) * Receive data register 4 (RDR4) * Shift Register 4 (SR4) 18.3.1 Serial Control Register 4 (SCR4)
SCR4 enables or disables interrupt requests and controls SCI4 transfer operations.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable Enables or disables a transmit data empty interrupt (TXI) request when serial transmit data is transferred from TDR4 to SR4 and the TDRE flag in SCSR4 is set to 1. TXI can be cleared by clearing the TDRE flag in SCSR4 to 0 after the flag is read as 1 or clearing this bit to 0. 0: Transmit data empty interrupt (TXI) request disabled 1: Transmit data empty interrupt (TXI) request enabled 6 RIE 0 R/W Receive Interrupt Enable Enables or disables a receive data full interrupt (RXI) request and receive error interrupt (ERI) request when serial receive data is transferred from SR4 to RDR4 and the RDRF flag in SCSR4 is set to 1. RXI and ERI can be cleared by clearing the RDRF or ORER flag in SCSR4 to 0 after the flag is read as 1 or clearing this bit to 0. 0: Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled 1: Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
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Section 18 Serial Communication Interface 4 (SCI4)
Bit 5
Bit Name TEIE
Initial Value 0
R/W R/W
Description Transmit End Interrupt Enable Enables or disables a transmit end interrupt (TEI) request when there is no valid transmit data in TDR4 during transmission of MSB data. TEI can be cleared by clearing the TEND flag in SCSR4 to 0 after the flag is read as 1 or clearing this bit to 0. 0: Transmit end interrupt (TEI) request disabled 1: Transmit end interrupt (TEI) request enabled
4
SOL
0
R/W
Extended Data Sets the output level of the SO4 pin. When this bit is read, the output level of the SO4 pin is read. The output of the SO4 pin retains the value of the last bit of transmit data after transmission is completed. However, if this bit is changed before or after transmission, the output level of the SO4 pin can be changed. When the output level of the SO4 pin is changed, the SOLP bit should be cleared to 0 and the MOV instruction should be used. Note that this bit should not be changed during transmission because incorrect operation may occur. [When reading] 0: The output level of the SO4 pin is low. 1: The output level of the SO4 pin is high. [When writing] 0: The output level of the SO4 pin is changed to low. 1: The output level of the SO4 pin is changed to high.
3
SOLP
1
R/W
SOL Write Protect Controls change of the output level of the SO4 pin due to the change of the SOL bit. When the output level of the SO4 pin is changed, the setting of SOL = 1 and SOLP = 0 or SOL = 0 and SOLP = 0 is made by the MOV instruction. This bit is always read as 1. 0: When writing, the output level is changed according to the value of the SOL pin. 1: When reading, this bit is always read as 1 and cannot be modified.
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Section 18 Serial Communication Interface 4 (SCI4)
Bit 2
Bit Name SRES
Initial Value 0
R/W R/W
Description Forcible Reset When the internal sequencer is forcibly initialized, 1 should be written to this bit. When 1 is written to this flag, the internal sequencer is forcibly reset and then this flag is automatically cleared to 0. Note that the values of the internal registers are retained. (The TDRE flag in SCSR4 is set to 1 and the RDRF, ORER, and TEND flags are cleared to 0. The TE and RE bits in SCR4 are cleared to 0.) 0: Normal operation 1: Internal sequencer is forcibly reset
1
TE
0
R/W
Transmit Enable Enables or disables start of the SCI4 serial transmission. When this bit is cleared to 0, the TERE flag in SCSR4 is fixed to 1. When transmit data is written to TDR4 while this bit is set to 1, the TDRE flag in SCSR4 is automatically cleared to 0 and serial data transmission is started. 0: Transmission disabled (SO4 pin functions as I/O port) 1: Transmission enabled (SO4 pin functions as transmit data pin)
0
RE
0
R/W
Receive Enable Enables or disables start of the SCI4 serial reception. Note that the RDRF and ORER flags in SCSR4 are not affected even if this bit is cleared to 0, and retain their previous state. Serial data reception is started when the synchronous clock input is detected while this bit is set to 1 (when an external clock is selected). When an internal clock is selected, the synchronous clock is output and serial data reception is started. 0: Reception disabled (SI4 pin functions as I/O port) 1: Reception enabled (SI4 pin functions as receive data pin)
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Section 18 Serial Communication Interface 4 (SCI4)
18.3.2
Serial Control/Status Register 4 (SCSR4)
SCSR4 indicates the operating state and error state, selects the clock source, and controls the prescaler division ratio. SCSR4 can be read from or written to by the CPU at any time. 1 cannot be written to flags TDRE, RDRF, ORER, and TEND. To clear these flags to 0, 1 should be read from them in advance.
Bit 7 Bit Name TDRE Initial Value 1 R/W Description
R/(W)* Transmit Data Empty Indicates that data is transferred from TDR4 to SR4 and the next serial transmit data can be written to TDR4. [Setting conditions] * * The TE bit in SCR4 is 0 Data is transferred from TDR4 to SR4 and data can be written to TDR4 Writing of 0 to bit TDRE after reading TDRE = 1 Data is written to TDR4
[Clearing conditions] * * 6 RDRF 0
R/(W)* Receive Data Full Indicates that the receive data is stored in RDR4. [Setting condition] * Serial reception ends normally and receive data is transferred from SR4 to RDR4 Writing of 0 to bit RDRF after reading RDRF = 1 Data is read from RDR4
[Clearing conditions] * *
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Section 18 Serial Communication Interface 4 (SCI4)
Bit 5
Bit Name ORER
Initial Value 0
R/W
Description
R/(W)* Overrun Error Indicates that an overrun error occurs during reception and then abnormal termination occurs. In transfer mode, the output level of the SO4 pin is fixed to low while this flag is set to 1. When the RE bit in SCR4 is cleared to 0, the ORER flag is not affected and retains its previous state. When RDR4 retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with the ORER flag set to 1, and transmission cannot be continued either. [Setting condition] * * Next serial reception is completed while RDRF = 1 Writing of 0 to bit ORER after reading ORER = 1 [Clearing condition]
4
TEND
0
R/(W)* Transmit End Indicates that the TDRE flag has been set to 1 at transmission of the last bit of transmit data. [Setting condition] * TDRE = 1 at transmission of the last bit of transmit data Writing of 0 to bit to TEND after reading TEND = 1 Data is written to TDR4 with an instruction
[Clearing conditions] * * 3 2 1 0 CKS3 CKS2 CKS1 CKS0 1 0 0 0 R/W R/W R/W R/W
Clock Source Select and Pin Function Select the clock source to be supplied and set the input/output for the SCK4 pin. The prescaler division ratio and transfer clock cycle when an internal clock is selected are shown in table 18.2. When an external clock is selected, the external clock cycle should be at least 4/.
Note:
*
Only 0 can be written to clear the flag.
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Section 18 Serial Communication Interface 4 (SCI4)
Table 18.2 shows a prescaler division ratio and transfer clock cycle. Table 18.2 Prescaler Division Ratio and Transfer Clock Cycle (Internal Clock)
Bit 3 CKS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 CKS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Prescaler Division Ratio /1024 /256 /64 /32 /16 /8 /4 /2 Transfer Clock Cycle = 5 MHz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s External clock Function Clock Source Internal clock Internal clock Internal clock Internal clock Internal clock Internal clock Internal clock Internal clock Pin Function SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin SCK4 output pin
I/O port (initial value) I/O port I/O port I/O port I/O port I/O port I/O port SCK4 input pin
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Section 18 Serial Communication Interface 4 (SCI4)
18.3.3
Transmit Data Register 4 (TDR4)
TDR4 is an 8-bit register that stores data for serial transmission. When the SCI4 detects that SR4 is empty, it transfers the transmit data written in TDR4 to SR4 and starts serial transmission. If the next transmit data is written to TDR4 while serial data in SR4 is being transmitted, continuous serial transmission is possible. TDR4 can be read from or written to by the CPU at any time. TDR4 is initialized to H'FF. 18.3.4 Receive Data Register 4 (RDR4)
RDR4 is an 8-bit register that stores receive data. When the SCI4 has received one byte of serial data, it transfers the received serial data from SR4 to RDR4, where it is stored. Then receive operation is completed. After this, SR4 is receive-enabled. RDR4 cannot be written to by the CPU. RDR4 is initialized to H'00. 18.3.5 Shift Register 4 (SR4)
SR4 is a register that receives or transmits serial data. SR4 cannot be directly read from or written to by the CPU.
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Section 18 Serial Communication Interface 4 (SCI4)
18.4
Operation
The SCI4 is a serial communication interface that transmits and receives data in synchronization with a clock pulse and is suitable for high-speed serial communications. The data transfer format is fixed to 8-bit data. The internal clock or external clock can be selected as a clock source. An overrun error during reception can be detected. The transmit and receive units are configured with double buffering mechanism. Since the mechanism enables to write data during transmission and to read data during reception, data is consecutively transmitted and received. 18.4.1 Clock
The eight internal clocks or an external clock can be selected as a transfer clock. When the external clock is selected, the SCK4 pin is a clock input pin. When the internal clock is selected, the SCK4 pin is a synchronous clock output pin. The synchronous clock is output eight pulses for 1-character transmission or reception. While neither transmission nor reception is being performed, the signal is fixed high. When the internal clock or external clock is not selected according to the combination of the CKS3 to CKS0 bits in SCSR4, the SCK4 pin functions as an I/O port. 18.4.2 Data Transfer Format
Figure 18.2 shows the SCI4 transfer format.
SCK4
SO4/SI4
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 18.2 Data Transfer Format In clock synchronous communication, data on the communication line is output from the falling edge to the next falling edge of the synchronous clock. The data is guaranteed to be settled at the rising edge of the synchronous clock. One character starts with the LSB and ends with the MSB. After transmitting the MSB, the communication line retains the MSB level. The SCI4 latches data at the rising edge of the synchronous clock on reception. The data transfer format is fixed to 8-bit data. While transmission is stopped, the output level on the SO4 pin can be changed by the SOL setting in SCR4.
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Section 18 Serial Communication Interface 4 (SCI4)
18.4.3
Data Transmission/Reception
Before data transmission and reception, clear the TE and RE bits in SCR4 to 0 and then initialize as the following procedure of figure 18.3. Note: Before changing operating modes or communication format, the TE and RE bits must be cleared to 0. Clearing the TE bit to 0 sets the TDRE flag to 1. Note that clearing the RE bit to 0 does not affect the RDRF or ORER flag and the contents of RDR4. When the external clock is used, the clock must not be supplied during operation including initialization.
Start of Initialization Clear TE and RE bits in SCR4 to 0 Clear CKS3 to CKS0 bits in SCSR4 to 0 Set TE and RE bits in SCR4 to 1. Set RIE, TIE, and TEIE bits.

Figure 18.3 Flowchart Example of SCI4 Initialization
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Section 18 Serial Communication Interface 4 (SCI4)
18.4.4
Data Transmission
Figure 18.4 shows an example flowchart of data transmission. Data transmission should be performed as the following procedure after the SCI4 initialization.
Initialization
[1] [1] Pin SO4 functions as output pin for transmit data After reading SCSR4 and confirming TDRE = 1, write transmit data in TDR4. Writing data in TDR4 clears the TDRE bit to 0 automatically. At this time, the clock is output to start data transmission. To consecutively transmit data, read TDRE = 1 to confirm that TDR4 is ready. After that, write data in TDR4. Writing data in TDR4 clears the TDRE bit to 0 automatically.
Start transmission (TE = 1)
[2] [2] [3]
Read TDRE in SCSR4
TDRE = 1? Yes Write transmit data in TDR4
No
TDRE bit cleared to 0 automatically
Data transferred from TDR4 to SR4 Start transmission by setting TDRE bit to 1
Transmission will continue? No Read TEND in SCSR4
Yes [3]
TEND = 1? Yes TEI occurs (TEIE = 1)
No
Clear TE bit in SCR4 to 0 Note: Hatching area indicates SCI internal operation.

Figure 18.4 Flowchart Example of Data Transmission
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Section 18 Serial Communication Interface 4 (SCI4)
During transmission, the SCI4 operates as shown below. 1. The SCI4 sets the TE bit to 1 and clears the TDRE flag to 0 when transmit data is written to in TDR4 to transmit data from TDR4 to SR4. After that, the SCI4 sets the TDRE flag to 1 to start transmission. At this time, when the TIE bit in SCR4 is set to 1, a TXI is generated. 2. In clock output mode, the SCI4 outputs eight pulses of the synchronous clock. When the external clock is selected, the SCI4 outputs data in synchronization with the input clock. 3. Serial data is output from the LSB (bit 0) to MSB (bit 7) on pin SO4. The SCI4 checks the TDRE flag at the timing of outputting the MSB (bit 7). 4. When TDRE = 0, data in TDR4 is transmitted to SR4 and then the data of the next frame starts to be transmitted. When TDRE = 1, the SCI4 sets the TEND bit to 1 and holds the output level after transmitting the MSB (bit 7). At this time, when the TEIE bit in SCR4 is set to 1, a TEI is generated. 5. After the transmission, the output level on pin SCK4 is fixed high. Note: Transmission cannot be performed when the error flag (ORER) which indicates the data reception status is set to 1. Before transmission, confirm that the ORER flag is cleared to 0. Figure 18.5 shows the example of transmission operation.
Synchronous clock
Serial data
Bit 0
Bit 1 1 frame
Bit 7
Bit 0
Bit 1 1 frame
Bit 6
Bit 7
TDRE
TEND TXI generated TDRE cleared Data written to TDR4 TXI generated TEI generated
LSI operation User operation
Figure 18.5 Transmit Operation Example
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Section 18 Serial Communication Interface 4 (SCI4)
18.4.5
Data Reception
Figure 18.6 shows an example flowchart of data reception. Data reception should be performed as the following procedure after the SCI4 initialization.
Initialization Start reception (RE = 1)
[1]
[1]
Read ORER in SCSR4
[2]
ORER = 1? No Read RDRF in SCSR4
Yes [3] Error processing (Shown below) [4]
Pin SI4 functions as input pin for receive data [2][3] When a reception error occurs, read the ORER flag in SCSR4 and then clears the ORER flag to 0 after executing the error processing. When the ORER flag is set to 1, both transmission and reception cannot be restarted. [4] After reading SCSR4 and confirming RDRF = 1, read the receive data in RDR4. The RDRF flag is automatically cleared to 0. Changes in the RDRF flag from 0 to 1 can be notified by an RXI interrupt. [5] To consecutively receive data, reading the RDRF flag and RDR4 must be completed before receiving the MSB (bit 7) of the current frame.
No
RDRF = 1? Yes Read received data in RDR4 RDRF cleared to 0 automatically
Yes
Data transfer will continue? No Clear RE bit in SCR4 to 0 Error processing Overrun error processing
[5]
[3]
Clear ORER flag in SCSR4 to 0 Note: Hatching area indicates SCI internal operation.
Figure 18.6 Flowchart Example of Data Reception
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Section 18 Serial Communication Interface 4 (SCI4)
During reception, the SCI4 operates as shown below. 1. The SCI4 initialization is performed in synchronization with the synchronous clock input or output and starts reception. 2. The SCI4 stores received data from the LSB to MSB of SR4. 3. After reception, the SCI4 checks that RDRF = 0 and whether receive data is ready for being transferred from SR4 to RDR4. 4. When confirms that an overrun error has not occurred, the RDRF bit is set to 1 and the received data is stored in RDR4. At this time, when the RIE bit in SCR4 is set to 1, an RXI is generated. When an overrun error is detected by checking, the ORER flag is set to 1. The RDRF bit retains the previously set value. If the RIE bit in SCR4 is set to 1, an ERI is generated. 5. An overrun error is detected when the next data reception is completed with the RDRF bit in SCSR4 set to 1. The received data is not transferred from SR4 to RDR4. Note: Reception cannot be performed when the error flag is set to 1. Before reception, confirm that the ORER and RDRF flags are cleared to 0. Figure 18.7 shows an operation example of reception.
Synchronous clock
Serial data
Bit 7
Bit 0 1 frame
Bit 7
Bit 0
Bit 1 1 frame
Bit 6
Bit 7
RDRF
ORER RXI generated RDRF cleared Data read from RDR4 RXI generated RDR4 has not been read from (RDRF = 1) ERI generated by overrun error Overrun error processing
LSI operation
User operation
Figure 18.7 Receive Operation Example
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Section 18 Serial Communication Interface 4 (SCI4)
18.4.6
Simultaneous Data Transmission and Reception
Figure 18.8 shows an example flowchart of simultaneous data transmission and reception. Simultaneous data transmission and reception should be performed as the following procedure after the SCI4 initialization.
[1] Pin SO4 functions as output pin for transmit data and pin SI4 functions as input pin for receive data. Simultaneous transmission and reception is enabled. After reading SCSR4 and confirming TDRE = 1, write transmit data in TDR4. Writing data in TDR4 clears the TDRE bit to 0 automatically. At this time, the clock is output to start data transfer. When a reception error occurs, read the ORER flag in SCSR4 and then clear the ORER flag to 0 after executing the error processing. When the ORER flag is set to 1, both transmission and reception cannot be restarted. After reading SCSR4 and confirming RDRF = 1, read receive data in RDR4 and clear the RDRF flag to 0. An RXI interrupt can also be used to confirm that the RDRF flag value has been changed from 0 to 1. To consecutively transmit and receive data, the following operation must be completed: reading the RDRF flag and reading RDR4 before receiving the MSB (bit 7) of the current frame: confirming that TDR4 is ready for writing by reading TDRE = 1 before transmitting the MSB (bit 7) and writing data to TDR4 to clear the TDRE flag to 0.
Initialization Start transmission (TE = 1, RE = 1)
[1]
[2] Read TDRE in SCSR4 [2]
TDRE = 1? Yes Write transmit data in TDR4
No
[3]
[4]
TDRE bit cleared to 0 automatically Data transferred from TDR4 to SR4 [5] Start transmission/reception by setting TDRE bit to 1 Read ORER in SCSR4
ORER = 1? No Read RDRF in SCSR4
Yes Error processing [4] [3]
No
RDRF = 1? Yes Read received data in RDR4 RDRF cleared to 0 automatically
Data transfer will continue? No Clear TE and RE bits in SCR4 to 0
Yes
[5]
Note: Hatching area indicates SCI internal operation.

Figure 18.8 Flowchart Example of Simultaneous Transmission and Reception
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Section 18 Serial Communication Interface 4 (SCI4)
Notes: 1. When switching from transmission to simultaneous data transmission and reception, confirm that the SCI4 completes transmission and both the TDRE and TEND bits are set to 1. After that, clear the TE bit to 0 and then set both the TE and RE bits to 1. 2. When switching from reception to simultaneous data transmission and reception, confirm that the SCI4 completes reception and both the RDRF and ORER flags are cleared to 0 after clearing the RE bit to 0. After that, set both the TE and RE bits to 1.
18.5
Interrupt Sources
The SCI4 has four interrupt sources: transmit end, transmit data empty, receive data full, and receive error (overrun error). Table 18.3 lists the descriptions of the interrupt sources. Table 18.3 SCI4 Interrupt Sources
Abbreviation RXI TXI TEI ERI Condition RIE = 1 TIE = 1 TEIE = 1 RIE = 1 Interrupt Source Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) Receive error (ORER)
The interrupt requests can be enabled/disabled by the TIE and RIE bits in SCR4. When the TDRE flag in SCSR4 is set to 1, a TXI is generated. When the TEND bit in SCSR4 is set to 1, a TEI is generated. These two interrupt requests are generated during transmission. The TDRE flag in SCSR4 is initialized to 1. Therefore, if a TXI request is enabled by setting the TIE bit in SCR4 to 1 before transmit data is transferred to TDR4, a TXI is generated even when transmit data is not ready. If transmit data is transferred to TDR4 in the interrupt handling routine, these interrupt requests can be effectively used. To avoid the occurrence of the interrupt requests (TXI and TEI), clear the corresponding interrupt enable bits (TIE and TEIE) to 0 after transmit data is transferred to TDR4. When the RDRF bit in SCSR4 is set to 1, an RXI is generated. When the ORER flag is set to 1, an ERI is generated. These two interrupt requests are generated during reception.
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Section 18 Serial Communication Interface 4 (SCI4)
18.6
Usage Notes
When using the SCI4, keep in mind the following. 18.6.1 Relationship between Writing to TDR4 and TDRE
The TDRE flag in SCSR4 is a status flag that indicates that data to be transmitted has not been stored in TDR4. When writing data to TDR4, the TDRE flag is automatically cleared to 0. The TDRE flag is set to 1 when the SCI4 transfers data from TDR4 to SR4. Data is written to TDR4 regardless of the TDRE flag value. However, if data is written to TDR4 with TDRE = 0, the previous data is lost unless the previous data has been transferred to SR4. Accordingly, to ensure transmission, writing transmit data to TDR4 must be performed once after confirming that the TDRE flag has been set to 1. (Do not write more than once.) 18.6.2 Receive Error Flag and Transmission
While the receive error flag (ORER) is set to 1, transmission cannot be started even if the TDRE flag is cleared to 0. To start transmission, the ORER flag must be cleared to 0. Note that the ORER flag cannot be cleared to 0 even if the RE bit is cleared to 0. 18.6.3 Relationship between Reading RDR4 and RDRF
The SCI4 always checks the RDRF flag status during reception. When the RDRF flag is cleared to 0 at the end of a frame, the reception is completed without error. When the RDRF flag is set to 1, it indicates that an overrun has occurred. Since reading RDR4 clears the RDRF flag to 0 automatically, if RDR4 is read twice or more, the data is read with the RDRF flag cleared to 0. In this case, when the timing of the read operation matches that of the data reception of the next frame, the read data may be the next frame data. Figure 18.9 shows this operation.
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Section 18 Serial Communication Interface 4 (SCI4)
Frame 1 Number of transfer Data 1
Frame 2 Data 2
Frame 3 Data 3
RDRF
RDR4
Data 1 (A) RDR4 read (B)
Data 2
RDR4 read
At the timing of (A), data 1 is read. At the timing of (B), data 2 is read.
Figure 18.9 Relationship between Reading RDR4 and RDRF In this case, RDR4 must be read only once after confirming RDRF = 1. If reading RDR4 twice or more, store the read data in the RAM, and use the stored data. In addition, there should be a margin from the timing of reading RDR4 to completion of the next frame reception (reading RDR4 should be completed before the bit 7 transfer). 18.6.4 SCK4 Output Waveform when Internal Clock of /2 is Selected
When the internal clock of /2 is selected by the CKS3 to CKS0 bits in SCSR4 and continuous transmission or reception is performed, one pulse of high period is lengthened after eight pulses of the clock has been output as shown in figure 18.10.
SCK4
SO4/SI4
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit0
Bit1
Bit2
Figure 18.10 Transfer Format when Internal Clock of /2 is Selected
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Section 18 Serial Communication Interface 4 (SCI4)
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Section 19 14-Bit PWM
Section 19 14-Bit PWM
This LSI has an on-chip 14-bit pulse width modulator (PWM) with four channels. Connecting the PWM to the low-pass filter enables the PWM to be used as a D/A converter. The standard PWM or pulse-division type PWM can be selected by software. Figure 19.1 shows a block diagram of the 14-bit PWM.
19.1
Features
* Choice of four conversion periods A conversion period of 131,072/ with a minimum modulation width of 8/, a conversion period of 65,536/ with a minimum modulation width of 4/, a conversion period of 32,768/ with a minimum modulation width of 2/, or a conversion period of 16,384/ with a minimum modulation width of 1/, can be selected. * Pulse division method for less ripple * Use of module standby mode enables this module to be placed in standby mode independently when not used (for details, refer to section 6.4, Module Standby Function). * The standard PWM or pulse-division type PWM can be selected by software.
PWDR
/2 /4 /8 /16
PWM waveform generator
PWCR PWM Pulse-division type waveform Standard waveform AEC [Legend] PWDR: PWCR: PWM data register PWM control register PWM waveform generator
Figure 19.1 Block Diagram of 14-Bit PWM
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Internal data bus
Section 19 14-Bit PWM
19.2
Input/Output Pins
Table 19.1 shows the 14-bit PWM pin configuration. Table 19.1 Pin Configuration
Pin Name PWM1 output pin PWM2 output pin PWM3 output pin PWM4 output pin Abbreviation PWM1 PWM2 PWM3 PWM4 I/O Output Output Output Output Function Standard PWM/pulse-division type PWM waveform output (PWM1) Standard PWM/pulse-division type PWM waveform output (PWM2) Standard PWM/pulse-division type PWM waveform output (PWM3) Standard PWM/pulse-division type PWM waveform output (PWM4)
19.3
Register Descriptions
The 14-bit PWM has the following registers. * PWM1 control register (PWCR1) * PWM1 data register (PWDR1) * PWM2 control register (PWCR2) * PWM2 data register (PWDR2) * PWM3 control register (PWCR3) * PWM3 data register (PWDR3) * PWM4 control register (PWCR4) * PWM4 data register (PWDR4)
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Section 19 14-Bit PWM
19.3.1
PWM Control Register (PWCR)
PWCR selects the input clocks and selects whether the standard PWM or pulse-division type PWM is used.
Bit 7 to 3 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 2 PWCRm2 0 W PWM Output Waveform Select Selects whether the standard PWM waveform or pulsedivision type PWM waveform is output. 0: Pulse-division type PWM waveform is output 1: Standard PWM waveform is output 1 0 PWCRm1 PWCRm0 0 0 W W Clock Select 1 and 0 Select the clock supplied to the 14-bit PWM. These bits are write-only bits and always read as 1. 00: The input clock is /2 A conversion period is 16,384/, with a minimum modulation width of 1/ 01: The input clock is /4 A conversion period is 32,768/, with a minimum modulation width of 2/ 10: The input clock is /8 A conversion period is 65,536/, with a minimum modulation width of 4/ 11: The input clock is /16 A conversion period is 131,072/, with a minimum modulation width of 8/ Note: m = 4 to 1
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Section 19 14-Bit PWM
19.3.2
PWM Data Register (PWDR)
PWDR is a 14-bit write-only register. PWDR indicates the high-level width in one pulse period of the PWM waveform when the pulse-division type PWM is selected. When data is written to the lower 14 bits of PWDR, the contents are latched in the PWM waveform generator and the PWM waveform generation data is updated. PWDR is initialized to 0 and always read as H'FFFF. Writing to this register should be in a word unit.
19.4
19.4.1
Operation
Principle of Pulse-Division Type PWM
In pulse-division type PWM, the high-level and low-level periods of the ordinary PWM waveform are divided and output alternately. This can reduce the ripples generated when the PWM module is used as a D/A converter by connecting a low-pass filter to it. Figure 19.2 shows an example of waveform when the pulse is divided into four. The 14-bit PWM module divides the pulse into 64.
One coversion period
Ordinary PWM
(1)
(2)
(3)
(4)
(5)
(6)
(7) (8)
Pulse-division type PWM (Example: When divided into four)
(1)
(5)
(2)
(6)
(3)
(7)
(4)
(8)
Figure 19.2 Example of Waveform Produced by Pulse-Division Type PWM (Division by 4)
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Section 19 14-Bit PWM
19.4.2
Setting for Pulse-Division Type PWM Operation
When using the pulse-division type PWM, set the registers in this sequence: 1. In accord with the PWM channel to be used, set the PWM1, PWM2, PWM3, or PWM4 bit (the former two bits are in PMR9 and the latter two in PFCR) to 1 to specify the P90/PWM1, P91/PWM2, P92/IRQ4/PWM3, or P93/PWM4 pin, respectively, to function as a PWM output pin. 2. Set PWCR to select a conversion period. 3. Set the data for output waveform in PWDR. When the data is written to PWDR, the contents are latched in the PWM waveform generator, and the PWM waveform generation data is updated. 19.4.3 Operation of Pulse-Division Type PWM
One conversion period consists of 64 pulses, as shown in figure 19.3. The total high-level width during this period (TH) corresponds to the data in PWDR. This relation is given in table 19.2.
One conversion period
tf1
tf2
tf63
tf64
tH1 tf1 = tf2 = tf3
tH2
. . . = tH64
tH3
tH63
tH64
TH = tH1 + tH2 + tH3 + . . . tH64
Figure 19.3 Waveform Output by PWM
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Section 19 14-Bit PWM
Table 19.2 Relationship between PWCR, PWDR and Output Waveform
PWCRm Setting Value PWCRm1 0 0 1 1 Note: PWCRm0 0 1 0 1 One Conversion TH [tcyc] Period [tcyc] 16384 32768 65536 131072 (PWDRm+64) x 1 (PWDRm+64) x 2 (PWDRm+64) x 4 (PWDRm+64) x 8 Tfn [tcyc] 256 512 1024 2048 Minimum Variation Width [tcyc] 1 2 4 8
m = 1 to 4, n = 1 to 64
19.4.4
Setting for Standard PWM Operation
When using the standard PWM, set the registers in this sequence: 1. According to the PWM channel used, set the PWM1, PWM2, PWM3, or PWM4 bit (the former two bits are in PMR9 and the latter two in PFCR) to 1 to set the P90/PWM1, P91/PWM2, P92/IRQ4/PWM3, or P93/PWM4 pin to function as a PWM pin. 2. Set PWCRm2 to 1 to select the standard PWM waveform. (m = 4 to 1) 3. Set the event counter PWM in the asynchronous event counter. For the setting method, see section 15.4.4, Event Counter PWM Operation. 4. The PWM pin outputs the PWM waveform set by the event counter. Note: When the standard waveform is used, 16-bit counter operation, 8-bit counter operation, and IRQAEC operation for the asynchronous event counter are not available because the PWM for the asynchronous event counter is used. When the IECPWM signal of the asynchronous event counter goes high, ECH and ECL increment. However, when the signal goes low, these counters stop. (For details, refer to section 15.4, Operation.)
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Section 19 14-Bit PWM
19.4.5
PWM Operating States
The states of PWM module registers in each operating mode are shown in table 19.3. Table 19.3 PWM Operating States
Operating Mode
PWCRm PWDRm
Reset
Reset Reset
Active
Functioning Functioning
Sleep
Watch
Subactive Subsleep Standby
Retained Retained Retained Retained Retained Retained
Module Standby
Retained Retained
Functioning Retained Functioning Retained
Note: m = 4 to 1
19.5
19.5.1
Usage Notes
Timing of Writing to PWDR and Reflection in the PWM Waveform
If the PWDR register is rewritten while a PWM waveform is output, the operation will be as follows depending on in which state of the PWM waveform the writing was performed. * During low level output: * During high level output: When the new value increases the duty cycle The new PWDR value is reflected immediately after writing. When the new value decreases the duty cycle * If the high-level width of the pulse at the time of rewriting exceeds the high-level width specified by the new PWDR value, a high level is output for a single pulse period. * If the high-level width of the pulse at the time of rewriting does not exceed the highlevel width specified by the new PWDR value, the new value is reflected immediately after writing. The new PWDR value is reflected from the next pulse.
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Section 19 14-Bit PWM
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Section 20 A/D Converter
Section 20 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 20.1.
20.1
Features
* 10-bit resolution * Input channels: Eight channels * High-speed conversion: 12.4 s per channel (in 10-MHz operation) * Sample and hold function * Conversion start method A/D conversion can be started by software and external trigger. * Interrupt source An A/D conversion end interrupt request can be generated. * Use of module standby mode enables this module to be placed in standby mode independently when it is not in use (for details, refer to section 6.4, Module Standby Function).
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Section 20 A/D Converter
ADTRG
AMR
AN0 AN1 AN2 AN4 AN5 AN6 AN7 + Comparator Reference voltage AVSS [Legend] AMR: ADSR: ADRR: IRRAD: A/D mode register A/D start register A/D result register A/D conversion end interrupt request flag IRRAD AVSS AVCC AN3 Multiplexer ADSR
Control logic
AVCC
ADRR
Figure 20.1 Block Diagram of A/D Converter
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Internal data bus
Section 20 A/D Converter
20.2
Input/Output Pins
Table 20.1 shows the input pins used by the A/D converter. Table 20.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 External trigger input pin Abbreviation AVcc AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input External trigger input that controls the A/D conversion start. Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input pins
20.3
Register Descriptions
The A/D converter has the following registers. * A/D result register (ADRR) * A/D mode register (AMR) * A/D start register (ADSR)
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Section 20 A/D Converter
20.3.1
A/D Result Register (ADRR)
ADRR is a 16-bit read-only register that stores the results of A/D conversion. The data is stored in the upper 10 bits of ADRR. ADRR can be read by the CPU at any time, but the ADRR value during A/D conversion is undefined. After A/D conversion is completed, the conversion result is stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial value of ADRR is undefined. ADRR should be read in word size. 20.3.2 A/D Mode Register (AMR)
AMR sets the A/D conversion time, and selects the external trigger and analog input pins.
Bit 7 6 Bit Name TRGE Initial Value 0 0 R/W R/W Description Reserved This bit is always read as 0 and cannot be modified. External Trigger Select Enables or disables the A/D conversion start by the external trigger input. 0: Disables the A/D conversion start by the external trigger input. 1: Starts A/D conversion at the rising or falling edge of the ADTRG pin The edge of the ADTRG pin is selected by the ADTRGNEG bit in IEGR. 5 4 CKS1 CKS0 0 0 R/W R/W Clock Select Selects the clock source for A/D conversion. 00: /8 (conversion time = 124 states (max.) (basic clock = )) 01: /4 (conversion time = 62 states (max.) (basic clock = )) 10: /2 (conversion time = 31 states (max.) (basic clock = )) 11: Not selectable (use prohibited)
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Section 20 A/D Converter
Bit 3 2 1 0
Bit Name CH3 CH2 CH1 CH0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Channel Select 3 to 0 Select the analog input channel. 00xx: No channel selected 0100: AN0 0101: AN1 0110: AN2 0111: AN3 1000: AN4 1001: AN5 1010: AN6 1011: AN7 11xx: Use prohibited The channel selection should be made while the ADSF bit is cleared to 0.
[Legend] x: Don't care
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Section 20 A/D Converter
20.3.3
A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Bit 7 Bit Name ADSF Initial Value 0 R/W R/W Description When this bit is set to 1, A/D conversion is started. When conversion is completed, the converted data is set in ADRR and at the same time this bit is cleared to 0. If this bit is written to 0, A/D conversion can be forcibly terminated. Resistor Ladder Select 0: Resistor ladder operational while the A/D converter is in the wait state 1: Resistor ladder not operational while the A/D converter is in the wait state Resistor ladder is always halted in standby mode, watch mode, module standby mode, or on reset. 5 to 0 All 1 Reserved These bits are always read as 1 and cannot be modified.
6
LADS
0
R/W
20.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing the conversion time or analog input channel, in order to prevent incorrect operation, first clear the bit ADSF to 0 in ADSR. 20.4.1 1. 2. 3. 4. A/D Conversion
A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1, according to software. When A/D conversion is completed, the result is transferred to the A/D result register. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2 is set to 1 at this time, an A/D conversion end interrupt request is generated. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF bit is automatically cleared to 0 and the A/D converter enters the wait state.
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Section 20 A/D Converter
20.4.2
External Trigger Input Timing
The A/D converter can also start A/D conversion by input of an external trigger signal. External trigger input is enabled at the ADTRG pin when the ADTSTCHG bit in PMRB is set to 1* and TRGE bit in AMR is set to 1. Then when the input signal edge designated in the ADTRGNEG bit in IEGR is detected at the ADTRG pin, the ADSF bit in ADSR will be set to 1, starting A/D conversion. Figure 20.2 shows the timing. Note: * The ADTRG input pin is shared with the TEST pin. Therefore when the pin is used as the ADTRG pin, reset should be cleared while the 0-fixed or 1-fixed signal is input to the TEST pin. Then the ADTSTCHG bit should be set to 1 after the TEST signal is fixed.
ADTRG (when ADTRGNEG = 0) ADSF A/D conversion
Figure 20.2 External Trigger Input Timing 20.4.3 Operating States of A/D Converter
Table 20.2 shows the operating states of the A/D converter. Table 20.2 Operating States of A/D Converter
Operating Mode
AMR ADSR ADRR
Reset
Reset Reset Retained*
Active
Sleep
Watch
Retained Retained Retained
Subactive
Retained Retained Retained
Subsleep
Retained Retained Retained
Standby
Retained Retained Retained
Module Standby
Retained Retained Retained
Functioning Functioning Functioning Functioning Functioning Functioning
Note:
*
Undefined at a power-on reset.
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Section 20 A/D Converter
20.5
Example of Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 20.3 shows the operation timing. 1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is stored in ADRR. At the same time bit ADSF is cleared to 0, and the A/D converter goes to the idle state. Bit IENAD = 1, so an A/D conversion end interrupt is requested. The A/D interrupt handling routine starts. The A/D conversion result is read and processed. The A/D interrupt handling routine ends.
2.
3. 4. 5. 6.
If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 20.4 and 20.5 show flowcharts of procedures for using the A/D converter.
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Interrupt (IRRAD) Set*
IENAD Set* Set*
ADSF
A/D conversion starts
Channel 1 (AN1) operating state Idle
A/D conversion (1)
Idle Read conversion result A/D conversion result (1)
A/D conversion (2)
Idle Read conversion result A/D conversion result (2)
ADRR
Figure 20.3 Example of A/D Conversion Operation
Note: * indicates instruction execution by software.
Section 20 A/D Converter
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REJ09B0309-0200
Section 20 A/D Converter
Start
Set A/D conversion speed and input channel
Disable A/D conversion end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0? Yes Read ADRR data
Yes
Perform A/D conversion? No End
Figure 20.4 Flowchart of Procedure for Using A/D Converter (Polling by Software)
Start
Set A/D conversion speed and input channel Enable A/D conversion end interrupt Start A/D conversion
A/D conversion end interrupt generated? No
Yes
Clear IRRAD bit in IRR2 to 0 Read ADRR data
Yes
Perform A/D conversion? No End
Figure 20.5 Flowchart of Procedure for Using A/D Converter (Interrupts Used)
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Section 20 A/D Converter
20.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 20.6). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 20.7). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 20.7). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 20 A/D Converter
Digital output
111 110 101 100 011 010 001 000 1 8
Ideal A/D conversion characteristic
Quantization error
2 8
3 8
4 8
5 8
6 8
7 FS 8 Analog input voltage
Figure 20.6 A/D Conversion Accuracy Definitions (1)
Digital output Full-scale error
Ideal A/D conversion characterist
Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage
Offset error
Figure 20.7 A/D Conversion Accuracy Definitions (2)
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Section 20 A/D Converter
20.7
20.7.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. As a countermeasure, with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 20.8). When converting a high-speed analog signal, a low-impedance buffer should be inserted. 20.7.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board.
This LSI Sensor output impedance up to 10 k Sensor input Low-pass filter C up to 0.1 F Cin = 15 pF
A/D converter equivalent circuit 10 k 48 pF
Figure 20.8 Example of Analog Input Circuit
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Section 20 A/D Converter
20.7.3 1. 2. 3.
Other Usage Notes
ADRR should be read only when the ADSF bit in ADSR is cleared to 0. Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. When A/D conversion is started after clearing module standby mode, wait for 10 clock cycles before starting A/D conversion.
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Section 21 LCD Controller/Driver
Section 21 LCD Controller/Driver
This LSI has an on-chip segment-type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel.
21.1
Features
* Display capacity
Duty Cycle Static 1/2 1/3 1/4 Internal Driver 40 SEG 40 SEG 40 SEG 40 SEG
* LCD RAM capacity 8 bits x 20 bytes (160 bits) * Word access to LCD RAM * The segment output pins can be used as ports. SEG40 to SEG1 pins can be used as ports in groups of four. * Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection). With 1/2 duty, parallel connection of COM1 to COM2, and of COM3 to COM4, can be used In static mode, parallel connection of COM1 to COM2, COM3, and COM4 can be used * Choice of 11 frame frequencies * A or B waveform selectable by software * On-chip power supply split-resistor * Display possible in operating modes other than standby mode * On-chip 3-V constant-voltage power supply circuit This power circuit can constantly supply 3 V to LCD drive power supply without using Vcc voltage. * Output of the 3-V constant-voltage power supply circuit adjustable * Use of module standby mode enables this module to be placed in standby mode independently when it is not in use (for details, see section 6.4, Module Standby Function).
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Section 21 LCD Controller/Driver
Figure 21.1 shows a block diagram of the LCD controller/driver.
Vcc C1 C2 V1 V2 V3 Vss /2 to /256 w, w/2, and w/4 Common data latch Common driver COM1 COM4
LCD drive power supply (On-chip 3-V constant-voltage power supply circuit)
LTRMR BGRMR LPCR
Internal data bus
LCR LCR2 40-bit shift register Segment driver
SEG40 SEG39 SEG38 SEG37 SEG36
Display timing generator
LCD RAM 20 bytes SEGn (n = 1 to 40) [Legend] LPCR: LCD port control register LCD control register LCR: LCR2: LCD control register 2 LTRMR: LCD trimming register BGRMR: BGR control register
SEG1
Figure 21.1 Block Diagram of LCD Controller/Driver
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Section 21 LCD Controller/Driver
21.2
Input/Output Pins
Table 21.1 shows the LCD controller/driver pin configuration. Table 21.1 Pin Configuration
Name Segment output pins Common output pins LCD power supply pins LCD step-up capacitance pins Symbol I/O Function LCD segment drive pins All pins are multiplexed as port pins (setting programmable) COM4 to COM1 Output LCD common drive pins Pins can be used in parallel with static or 1/2 duty V1, V2, V3 -- Used when a bypass capacitor is connected externally, and when an external power supply circuit is used Capacitance pins for stepping up the LCD drive power supply
SEG40 to SEG1 Output
C1, C2
--
21.3
Register Descriptions
The LCD controller/driver has the following registers. * LCD port control register (LPCR) * LCD control register (LCR) * LCD control register 2 (LCR2) * LCD trimming register (LTRMR) * BGR control register (BGRMR) * LCDRAM
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Section 21 LCD Controller/Driver
21.3.1
LCD Port Control Register (LPCR)
LPCR selects the duty cycle, LCD driver, and pin functions.
Bit 7 6 5 Bit Name DTS1 DTS0 CMX Initial Value 0 0 0 R/W R/W R/W R/W Description Duty Cycle Select 1 and 0 Common Function Select The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used due to the selected duty. For details, see table 21.2. 4 3 2 1 0 -- SGS3 SGS2 SGS1 SGS0 1 0 0 0 0 -- R/W R/W R/W R/W Reserved This bit is always read as 1 and cannot be modified. Segment Driver Select 3 to 0 Select the segment drivers to be used. For details, see table 21.3.
Table 21.2 Duty Cycle and Common Function Selection
Bit 7: DTS1 0 Bit 6: DTS0 0 Bit 5: CMX 0 1 Duty Cycle Static Common Drivers COM1 COM4 to COM1 Notes Do not use COM4, COM3, and COM2 COM4, COM3, and COM2 output the same waveform as COM1 Do not use COM4 and COM3 COM4 outputs the same waveform as COM3, and COM2 outputs the same waveform as COM1 Do not use COM4 Do not use COM4 --
1
0 1
1/2 duty
COM2 to COM1 COM4 to COM1
1
0 1
0 1 x
1/3 duty 1/4 duty
COM3 to COM1 COM4 to COM1 COM4 to COM1
[Legend] x: Don't care
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Section 21 LCD Controller/Driver
Table 21.3 Segment Driver Selection
Function of Pins SEG40 to SEG1 Bit 3: Bit 2: Bit 1: Bit 0: SEG40 SGS3 SGS2 SGS1 SGS0 to SEG37 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Port Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG SEG36 to SEG33 Port Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG SEG32 to SEG29 Port Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG SEG28 to SEG25 Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port SEG24 to SEG21 Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port SEG20 to SEG17 Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port SEG16 to SEG13 Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port SEG12 to SEG9 Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port SEG8 to SEG5 Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port SEG4 to SEG1 Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port
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Section 21 LCD Controller/Driver
21.3.2
LCD Control Register (LCR)
LCR controls LCD drive power supply and display data, and selects the frame frequency.
Bit 7 6 Bit Name -- PSW Initial Value 1 0 R/W -- R/W Description Reserved This bit is always read as 1 and cannot be modified. LCD Drive Power Supply Control Can be used to turn off the LCD drive power supply when LCD display is not required in power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0 or in standby mode, the LCD drive power supply is turned off regardless of the setting of this bit. 0: LCD drive power supply is turned off 1: LCD drive power supply is turned on 5 ACT 0 R/W Display Function Activate Specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless of the setting of the PSW bit. However, register contents are retained. 0: LCD controller/driver halts 1: LCD controller/driver operates 4 DISP 0 R/W Display Data Control Specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. 0: Blank data is displayed 1: LCD RAM data is displayed 3 2 1 0 CKS3 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W Frame Frequency Select 3 to 0 Select the operating clock and the frame frequency. However, in subactive mode, watch mode, and subsleep mode, the system clock () is halted. Therefore display operations are not performed if one of the clocks from /2 to /256 is selected. If LCD display is required in these modes, W, W/2, or W/4 must be selected as the operating clock. For details, see table 21.4.
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Section 21 LCD Controller/Driver
Table 21.4 Frame Frequency Selection
Bit 3: CKS3 0 Bit 2: CKS2 x Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 1 0 0 x 0 1 1 0 1 1 0 0 1 1 0 1 Frame Frequency* Operating Clock W W/2 W/4 /2 /4 /8 /16 /32 /64 /128 /256 = 2 MHz 128 Hz* 64 Hz* 32 Hz* -- 977 Hz 488 Hz 244 Hz 122 Hz 61 Hz 30.5 Hz --
2 2 2 2 1
= 250 kHz* 128 Hz* 64 Hz* 32 Hz*
2 2
3
244 Hz 122 Hz 61 Hz 30.5 Hz -- -- -- --
[Legend] x: Don't care Notes: 1. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 2. This is the frame frequency when W = 32.768 kHz. 3. This is the frame frequency in active (medium-speed, OSC/8) mode when OSC = 2 MHz.
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Section 21 LCD Controller/Driver
21.3.3
LCD Control Register 2 (LCR2)
LCR2 controls switching between the A waveform and B waveform, selection of the step-up clock for the 3-V constant-voltage circuit, connection with the LCD power-supply split resistor, and turning on or off 3-V constant-voltage power supply.
Bit 7 Bit Name LCDAB Initial Value 0 R/W R/W Description A Waveform/B Waveform Switching Control Specifies whether the A waveform or B waveform is used as the LCD drive waveform. 0: Drive using A waveform 1: Drive using B waveform 6 HCKS 0 R/W Step-Up Clock Selection for 3-V Constant-Voltage Power Supply Circuit Selects a step-up clock for use in the 3-V constantvoltage power supply circuit. The step-up clock is obtained by dividing the clock selected by the CKS3 to CKS0 bits in LCR into 4 or 8. 0: Divided into 4 1: Divided into 8 5 CHG 0 R/W Connection Control of LCD Power-Supply Split Resistor Selects whether an LCD power-supply split resistor is disconnected or connected from or to LCD drive power supply. 0: Disconnected 1: Connected 4 SUPS 0 R/W 3-V Constant-Voltage Power Supply Control Can be used to turn off the 3-V constant-voltage power supply when LCD display is not required in power-down mode, or when an external power supply is used. When the BGRSTPN bit in BGRMR is cleared to 0 or in standby mode, the 3-V constant-voltage power supply is turned off regardless of the setting of this bit. 0: 3-V constant-voltage power supply is turned off 1: 3-V constant-voltage power supply is turned on 3 to 0 -- 1 -- Reserved These bits are always read as 1 and cannot be modified.
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Section 21 LCD Controller/Driver
21.3.4
LCD Trimming Register (LTRMR)
LTRMR adjusts the 3-V constant-voltage used for LCD drive power supply and the output voltage of 3-V constant-voltage power supply circuit.
Bit 7 6 5 4 Bit Name TRM3 TRM2 TRM1 TRM0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Output Voltage Adjustment of 3-V Constant-Voltage 12 Power Supply Circuit* * By adjusting reference voltage that generates 3-V constant voltage, LCD drive power supply can be set to 3 V. Following values* indicate the voltage of the V1 pin. Set this register so that the voltage on the V1 pin should be 3 V. 0000: 0 V 1000: 0.48 V 0001: -0.06 V 1001: 0.42 V 0010: -0.12 V 1010: 0.36 V 0011: -0.15 V 1011: 0.30 V 0100: -0.21 V 1100: 0.24 V 0101: -0.24 V 1101: 0.18 V 0110: -0.30 V 1110: 0.12 V 0111: -0.33 V 1111: 0.06 V 3 -- 1 -- Reserved This bit is always read as 1 and cannot be modified.
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Section 21 LCD Controller/Driver
Bit 2 1 0
Bit Name CTRM2 CTRM1 CTRM0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Variable Voltage Adjustment of 3-V Constant-Voltage 12 Power Supply* * The LCD drive power supply adjusted by the TRM bits can further be adjusted. If an LCD panel does not function normally due to a temperature in which LCD is used, set these bits to adjust it. 000: 0 V 001: 0.09 V 010: 0.18 V 011: 0.27 V 100: -0.36 V 101: -0.27 V 110: -0.18 V 111: -0.09 V
Note:
1. These are approximate values and are not guaranteed. That is, the values are for reference only. 2. Setting of LTRMR The standard of the voltage after it trims becomes the following. V1 Initial state output voltage :A LTRMR Register TRM3 to TRM0 :B LTRMR Register CTRM3 to CTRM0 : C V1 Output voltage = A + B + C V2 Output voltage = (A + B + C)*2/3 V3 Output voltage = (A + B + C)/3 Please set A, B, and C so that the V1 voltage may become 3-V.
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Section 21 LCD Controller/Driver
21.3.5
BGR Control Register (BGRMR)
BGRMR controls whether the band-gap reference circuit (BGR) which generates the reference voltage of the 3-V constant-voltage power supply operates or halts, and adjusts the reference voltage.
Bit 7 Bit Name BGRSTPN Initial Value 0 R/W R/W Description Band-Gap Reference Circuit Control Controls whether the band-gap reference circuit operates or halts. 0: Band-gap reference circuit halts 1: Band-gap reference circuit operates 6 to 3 All 1 Reserved These bits are always read as 1 and cannot be modified. 2 1 0 BTRM2 BTRM1 BTRM0 0 0 0 R/W R/W R/W BGR Output Voltage Trimming BGR Output Voltage Trimming Adjust approximately 1.2-V BGR output voltage. 000: 0 V 001: +0.14 V 010: +0.09 V 011: +0.04 V 100: -0.04 V 101: -0.09 V 110: -0.14 V 111: -0.18 V
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Section 21 LCD Controller/Driver
21.4
21.4.1
Operation
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be determined. (1) (a) Hardware Settings Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 21.2.
VCC V1 V2 V3 VSS
Figure 21.2 Handling of LCD Drive Power Supply when Using 1/2 Duty (b) Large-Panel Display
As the impedance of the on-chip power supply split-resistor is large, it may not be suitable for driving a panel which requires a current more than the current value calculated by the on-chip power supply split-resistor and voltage of the LCD power supply. If the display lacks sharpness when using a large panel, refer to section 21.4.5, Boosting LCD Drive Power Supply and Fine Adjustment. When static or 1/2 duty is selected, the common output drive capability can be increased. Set CMX to 1 when selecting the duty cycle. In this mode, with a static duty cycle pins COM4 to COM1 output the same waveform, and with 1/2 duty the COM1 waveform is output from pins COM2 and COM1, and the COM2 waveform is output from pins COM4 and COM3.
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Section 21 LCD Controller/Driver
(c)
LCD Drive Power Supply Setting
With this LSI, there are two ways of providing LCD power: by using the on-chip power supply circuit, or by using an external power supply circuit. When an external power supply circuit is used for the LCD drive power supply, connect the external power supply to the V1 pin. (2) (a) Software Settings Duty Selection
Any of four duty cycles--static, 1/2 duty, 1/3 duty, or 1/4 duty--can be selected with bits DTS1 and DTS0. (b) Segment Driver Selection
The segment drivers to be used can be selected with bits SGS3 to SGS0. (c) Frame Frequency Selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency should be selected in accordance with the LCD panel specification. For the clock selection method in watch mode, subactive mode, and subsleep mode, see section 21.4.4, Operation in Power-Down Modes. (d) A or B Waveform Selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of LCDAB. (e) LCD Drive Power Supply Selection
When an external power supply circuit is used, turn the LCD drive power supply off with the PSW bit.
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Section 21 LCD Controller/Driver
21.4.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 21.3 to 21.6. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7 H'FFF360 SEG2 Bit 6 SEG2 Bit 5 SEG2 Bit 4 SEG2 Bit 3 SEG1 Bit 2 SEG1 Bit 1 SEG1 Bit 0 SEG1
H'FFF373
SEG40 COM4
SEG40 COM3
SEG40 COM2
SEG40 COM1
SEG39 COM4
SEG39 COM3
SEG39 COM2
SEG39 COM1
Figure 21.3 LCD RAM Map (1/4 Duty)
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Section 21 LCD Controller/Driver
Bit 7 H'FFF360
Bit 6 SEG2
Bit 5 SEG2
Bit 4 SEG2
Bit 3
Bit 2 SEG1
Bit 1 SEG1
Bit 0 SEG1
H'FFF373
SEG40 COM3
SEG40 COM2
SEG40 COM1
SEG39 COM3
SEG39 COM2
SEG39 COM1
Space not used for display
Figure 21.4 LCD RAM Map (1/3 Duty)
Bit 7 H'FFF360 SEG4 Bit 6 SEG4 Bit 5 SEG3 Bit 4 SEG3 Bit 3 SEG2 Bit 2 SEG2 Bit 1 SEG1 Bit 0 SEG1
Display space
H'FFF369
SEG40
SEG40 SEG39
SEG39
SEG38
SEG38
SEG37
SEG37
Space not used for display
H'FFF373 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1
Figure 21.5 LCD RAM Map (1/2 Duty)
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Section 21 LCD Controller/Driver
Bit 7 H'FFF360 SEG8
Bit 6 SEG7
Bit 5 SEG6
Bit 4 SEG5
Bit 3 SEG4
Bit 2 SEG3
Bit 1 SEG2
Bit 0 SEG1 Display space
H'FFF364
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
Space not used for display
H'FFF373 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
Figure 21.6 LCD RAM Map (Static Mode)
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Section 21 LCD Controller/Driver
Figure 21.7 shows output waveforms for each duty cycle (A waveform).
1 frame M Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS (a) Waveform with 1/4 duty 1 frame M Data COM1 V1 V2,V3 VSS V1 V2,V3 VSS V1 V2,V3 VSS (c) Waveform with 1/2 duty M Data V1 COM1 VSS V1 SEGn VSS (d) Waveform with static output M: LCD alternation signal V1 V2 V3 VSS (b) Waveform with 1/3 duty 1 frame M Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame
COM1
COM1
COM2
COM2
COM3
COM3
COM4
SEGn
SEGn
COM2
SEGn
Figure 21.7 Output Waveforms for Each Duty Cycle (A Waveform)
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Section 21 LCD Controller/Driver
Figure 21.8 shows output waveforms for each duty cycle (B waveform).
1 frame 1 frame 1 frame 1 frame M Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS (a) Waveform with 1/4 duty V1 V2 V3 VSS (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame 1 frame M Data V1 V2,V3 VSS V1 V2,V3 VSS V1 V2,V3 VSS (c) Waveform with 1/2 duty V1 COM1 VSS V1 SEGn VSS (d) Waveform with static output M: LCD alternation signal M Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame 1 frame 1 frame 1 frame
COM1
COM1
COM2
COM2
COM3
COM3
COM4
SEGn
SEGn
1 frame 1 frame 1 frame 1 frame M Data COM1
COM2
SEGn
Figure 21.8 Output Waveforms for Each Duty Cycle (B Waveform)
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Section 21 LCD Controller/Driver
Table 21.5 shows output levels. Table 21.5 Output Levels
Data M Static Common output Segment output 1/2 duty Common output Segment output 1/3 duty Common output Segment output 1/4 duty M: Common output Segment output LCD alternation signal 0 0 V1 V1 V2, V3 V1 V3 V2 V3 V2 0 1 VSS VSS V2, V3 VSS V2 V3 V2 V3 1 0 V1 VSS V1 VSS V1 VSS V1 VSS 1 1 VSS V1 VSS V1 VSS V1 VSS V1
21.4.3
3-V Constant-Voltage Power Supply Circuit
This LSI incorporates a 3-V constant-voltage power supply circuit consisting of a band gap reference circuit (BGR), a triple step-up circuit, etc. This allows the 3 V constant voltage to drive LCD driver independently of Vcc. Before activating a step-up circuit, operate the LCD controller/driver, and set the duty cycle, pin function, display data, frame frequencies, etc. Insert a capacitance of 0.1 F between the C1 pin and C2 pin, and connect a capacitance of 0.1 F to each of V1, V2, and V3 pins. (See figure 21.9.) After this setting, setting the BGRSTPN bit in the BGR control register (BGRMR) to 1 activates the band gap reference circuit, generating 1 V constant voltage (VLCD3) at the V3 pin. Furthermore, selecting the step-up circuit clock of the LCD control register 2 (LCR2) and setting the SUPS bit to 1 activates the triple step-up circuit, generating 2 V constant voltage, twice VLCD3, at the V2 pin, and generating 3 V constant voltage, triple VLCD3, at the V1 pin.
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Section 21 LCD Controller/Driver
Notes: 1. Power supply might be insufficient when a large panel is driven. In this case, use Vcc for power supply, or use an external power supply circuit. 2. Do not use a polarized capacitance such as an electrolytic capacitor for connection between the C1 pin and C2 pin. 3. A 3-V constant-voltage power supply circuit is turned on by SUSP bit regardless of the setting of the PSW bit. 4. The step-up circuit output voltage in the initial state is different in an individual device according to the manufacturing difference. Please set and adjust LCD trimming register (LTRMR) of each individual device.
C1 C2 V1 V2 V3 C C C C
C: 0.1 F
Figure 21.9 Capacitance Connection when Using 3-V Constant-Voltage Power Supply Circuit 21.4.4 Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 21.6. In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless W, W/2, or W/4 has been selected by bits CKS3 to CKS0, the clock will not be supplied and display will halt. The subclock can be turned on or off by setting the 32KSTOP bit in the SUB32k control register (SUB32CR). When it is turned off, display will halt. Since there is a possibility that a direct current will be applied to the LCD panel in this case, it is essential to ensure that the subclock is turned on and W, W/2, or W/4 is selected. In active (medium-speed) mode, the system clock is switched, and therefore bits CKS3 to CKS0 must be modified to ensure that the frame frequency does not change.
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Section 21 LCD Controller/Driver
Table 21.6 Power-Down Modes and Display Operation
Module Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby
Clock
w
Functioning Functioning Functioning Halted Functioning Functioning Functioning Functioning* Halted Displayed Halted Displayed Halted Displayed* *
35 5
Halted
5
Halted
5
Halted
1
Halted* Halted* Halted Halted
4
Functioning* Functioning* Halted* Halted Displayed* *
35
4
Display operation
ACT = 0 Halted ACT = 1 Halted
Halted Displayed* *
35
Halted*
2
Halted*
2
Notes: 1. The subclock oscillator does not stop, but clock supply is halted. 2. The LCD drive power supply is turned off regardless of the setting of the PSW bit. 3. Display operation is performed only if W, W/2, or W/4 is selected as the operating clock. 4. The clock supplied to the LCD stops. 5. When the 32KSTOP bit in SUB32CR is set to 1, the subclock W halts and display operation halts.
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Section 21 LCD Controller/Driver
21.4.5
Boosting LCD Drive Power Supply and Fine Adjustment
When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case, the power supply impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 F to pins V1 to V3, as shown in figure 21.10, or by adding a split resistor externally. The voltage on the V1 pin can further be adjusted by connecting a variable resistor (VR) between the VCC and V1 pins.
VCC V1
VR
R This LSI V2 R V3 R VSS
R = several k to several M
C = 0.1 to 0.3 F
Figure 21.10 Connection of External Split Resistor
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Section 21 LCD Controller/Driver
21.5
21.5.1 (1)
Usage Notes
Pin Handling when LCD Controller/Driver is not Used
V1, V2, and V3 Pins
Connect these pins to the GND, though the CHG bit in LCR2 should not be changed from the initial value of 0. (The split resistor should be left disconnected.) (2) C1 and C2 Pins
These pins should be left open. 21.5.2 Pin Handling when 3-V Constant-Voltage Power Supply Circuit is not Used
The C1 and C2 pins should be left open.
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Section 21 LCD Controller/Driver
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Section 22 I2C Bus Interface 2 (IIC2)
Section 22 I C Bus Interface 2 (IIC2)
The I C bus interface 2 conforms to and provides a subset of the Philips I C bus (inter-IC bus) 2 interface functions. The register configuration that controls the I C bus differs partly from the 2 Philips configuration, however. Figure 22.1 shows a block diagram of the I C bus interface 2. Figure 22.2 shows an example of I/O pin connections to external circuits.
2 2
2
22.1
Features
2
* Selection of I C format or clock synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. * Use of module standby mode enables this module to be placed in standby mode independently when not used (for details, refer to section 6.4, Module Standby Function). I C bus format * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, SCL and SDA pins, function as CMOS outputs in normal operation (when the port/serial function is selected) and NMOS outputs when the bus drive function is selected. Clock synchronous format * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error
2
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Section 22 I2C Bus Interface 2 (IIC2)
Transfer clock generation circuit
SCL
Output control
Transmission/ reception control circuit
ICCR1 ICCR2 ICMR
Noise canceler ICDRT SAR
SDA
Output control
ICDRS
Noise canceler
Address comparator ICDRR Bus state decision circuit Arbitration decision circuit
ICSR ICIER Interrupt generator
[Legend] ICCR1: ICCR2: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus interrupt enable register I2C bus transmit data register I2C bus receive data register I2C bus shift register Slave address register
Figure 22.1 Block Diagram of I C Bus Interface 2
2
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Internal data bus
Interrupt request
Section 22 I2C Bus Interface 2 (IIC2)
Vcc SCL
Vcc SCL
SCL in SCL out
SDA in SDA out (Master)
SDA
SDA
SCL SDA
SCL in SCL out
SCL in SCL out
SDA in SDA out (Slave 1)
SDA in SDA out (Slave 2)
Figure 22.2 External Circuit Connections of I/O Pins
22.2
Input/Output Pins
2
Table 22.1 shows the input/output pins of the I C bus interface 2. Table 22.1 Pin Configuration
Pin Name Serial clock pin Serial data pin Abbreviation SCL SDA I/O I/O I/O Function IIC serial clock input/output IIC serial data input/output
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SCL SDA
Section 22 I2C Bus Interface 2 (IIC2)
22.3
2
Register Descriptions
The I C bus interface 2 has the following registers. * I C bus control register 1 (ICCR1)
2 2 2 2 2
* I C bus control register 2 (ICCR2) * I C bus mode register (ICMR) * I C bus interrupt enable register (ICIER) * I C bus status register (ICSR) * Slave address register (SAR) * I C bus transmit data register (ICDRT)
2 2 2
* I C bus receive data register (ICDRR) * I C bus shift register (ICDRS) 22.3.1 I C Bus Control Register 1 (ICCR1)
2 2
ICCR1 enables or disables the I C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I C Bus Interface 2 Enable 0: This module is halted. (SCL and SDA pins are set to the port/serial function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception
2
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Section 22 I2C Bus Interface 2 (IIC2)
Bit 5 4
Bit Name MST TRS
Initial Value 0 0
R/W R/W R/W
Description Master/Slave Select Transmit/Receive Select In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. After data reception has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is automatically set to 1. If an overrun error occurs in master mode with the clock synchronous serial format, MST is cleared to 0 and slave receive mode is entered. Operating modes are described below according to MST and TRS combination. When clock synchronous serial format is selected and MST is 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode
2
3 2 1 0
CKS3 CKS2 CKS1 CKS0
0 0 0 0
R/W R/W R/W R/W
Transfer Clock Select 3 to 0 In master mode, set these bits according to the necessary transfer rate (see table 22.2, Transfer Rate). In slave mode, these bits are used to secure the data setup time in transmission mode. When CKS3 = 0, the data setup time is 10 tcyc and when CKS3 = 1, the data setup time is 20 tcyc.
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Section 22 I2C Bus Interface 2 (IIC2)
Table 22.2 Transfer Rate
Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 1 0 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256
= 2 MHz
Transfer Rate
= 5 MHz = 10 MHz
71.4 kHz 50.0 kHz 41.7 kHz 31.3 kHz 25.0 kHz 20.0 kHz 17.9 kHz 15.6 kHz 35.7 kHz 25.0 kHz 20.8 kHz 15.6 kHz 12.5 kHz 10.0 kHz 8.9 kHz 7.8 kHz
179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz
357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz
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Section 22 I2C Bus Interface 2 (IIC2)
22.3.2
I C Bus Control Register 2 (ICCR2)
2
ICCR1 issues start/stop conditions, handles the SDA pin, monitors the SCL pin, and controls reset 2 in the control part of the I C bus interface 2.
Bit 7 Bit Name BBSY Initial Value 0 R/W R/W Description Bus Busy This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. This bit has no functional role when the clock synchronous serial format is selected. When the 2 I C bus format is selected, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. The same procedure also applies to re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. To issue start/stop conditions, use the MOV instruction. 6 SCP 1 R/W Start/Stop Issue Condition Disable The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R/W SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance).
2
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Section 22 I2C Bus Interface 2 (IIC2)
Bit 4
Bit Name SDAOP
Initial Value 1
R/W R/W
Description SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1.
3
SCLO
1
R
This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. Reserved This bit is always read as 1. IIC Control Part Reset This bit resets the control part except for I C registers. If this bit is set to 1 when hang-up occurs because of 2 2 communication failure during I C operation, I C control part can be reset without setting ports and initializing registers.
2
2 1
IICRST
1 0
R/W
0
1
Reserved This bit is always read as 1.
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Section 22 I2C Bus Interface 2 (IIC2)
22.3.3
I C Bus Mode Register (ICMR)
2
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit In master mode with the I C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode with the 2 I C bus format or with the clock synchronous serial format. 5, 4 3 BCWP All 1 1 R/W Reserved These bits are always read as 1. BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid.
2 2
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Section 22 I2C Bus Interface 2 (IIC2)
Bit 2 1 0
Bit Name BC2 BC1 BC0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits 2 is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL pin is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. With the clock synchronous serial format, these bits should not be modified. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits
2
Clock Synchronous Serial Format 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits
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Section 22 I2C Bus Interface 2 (IIC2)
22.3.4
I C Bus Interrupt Enable Register (ICIER)
2
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) with the clock synchronous format, when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clock synchronous format are disabled. 1: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clock synchronous format are enabled.
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Section 22 I2C Bus Interface 2 (IIC2)
Bit 4
Bit Name NAKIE
Initial Value 0
R/W R/W
Description NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clock synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
3
STIE
0
R/W
Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgment Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted.
1
ACKBR
0
R
Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
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Section 22 I2C Bus Interface 2 (IIC2)
22.3.5
I C Bus Status Register (ICSR)
2
ICSR performs confirmation of interrupt request flags and status.
Bit 7 Bit Name TDRE Initial Value 0 R/W Description
R/(W)* Transmit Data Register Empty [Setting conditions] * * * * Data is transferred from ICDRT to ICDRS and ICDRT becomes empty TRS is set A start condition (including re-transfer) has been issued Transmit mode is entered from receive mode in slave mode Writing of 0 to bit TDRE after reading TDRE = 1 Data is written to ICDRT with an instruction
[Clearing conditions] * * 6 TEND 0
R/(W)* Transmit End [Setting conditions] * * The ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 The final bit of transmit frame is sent with the clock synchronous serial format Writing of 0 to bit TEND after reading TEND = 1 Data is written to ICDRT with an instruction
2
[Clearing conditions] * * 5 RDRF 0
R/(W)* Receive Data Register Full [Setting condition] * * * A receive data is transferred from ICDRS to ICDRR Writing of 0 to bit RDRF after reading RDRF = 1 ICDRR is read with an instruction [Clearing conditions]
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Section 22 I2C Bus Interface 2 (IIC2)
Bit 4
Bit Name NACKF
Initial Value 0
R/W
Description
R/(W)* No Acknowledge Detection Flag [Setting condition] * No acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 Writing of 0 to bit NACKF after reading NACKF = 1
[Clearing condition] * 3 STOP 0 R/(W)* Stop Condition Detection Flag [Setting conditions] * * In master mode, a stop condition is detected after frame transferred In slave mode, the slave address in the first byte after the general call and detecting start condition matches the address set in SAR, and then the stop condition is detected Writing of 0 to bit STOP after reading STOP = 1
[Clearing condition] * 2 AL/OVE 0 R/(W)* Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master 2 mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clock synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * * * The internal SDA and SDA pin disagree at the rise of SCL in master transmit mode The SDA pin outputs high in master mode while a start condition is detected The final bit is received with the clock synchronous format while RDRF = 1 Writing of 0 to bit AL/OVE after reading AL/OVE=1
[Clearing condition] *
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Section 22 I2C Bus Interface 2 (IIC2)
Bit 1
Bit Name AAS
Initial Value 0
R/W
Description
R/(W)* Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * * The slave address is detected in slave receive mode The general call address is detected in slave receive mode Writing of 0 to bit AAS after reading AAS=1
2
[Clearing condition] * 0 ADZ 0 R/(W)* General Call Address Recognition Flag This bit is valid in I C bus format slave receive mode. [Setting condition] * The general call address is detected in slave receive mode Writing of 0 to bit ADZ after reading ADZ=1
[Clearing conditions] * Note: * Only 0 can be written to clear the flag.
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Section 22 I2C Bus Interface 2 (IIC2)
22.3.6
Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode 2 with the I C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Bit 7 to 1 Bit Name SVA6 to SVA0 Initial Value All 0 R/W R/W Description Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing form the addresses of other slave devices 2 connected to the I C bus. 0 R/W Format Select 0: I C bus format is selected. 1: Clock synchronous serial format is selected.
2
0
FS
22.3.7
I C Bus Transmit Data Register (ICDRT)
2
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of ICDRT is H'FF. 22.3.8 I C Bus Receive Data Register (ICDRR)
2
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is H'FF. 22.3.9 I C Bus Shift Register (ICDRS)
2
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU.
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Section 22 I2C Bus Interface 2 (IIC2)
22.4
2
Operation
2
The I C bus interface 2 can communicate either in I C bus mode or clock synchronous serial mode by setting the FS bit in the slave address register (SAR). 22.4.1 I C Bus Format
2 2 2
Figure 22.3 shows the I C bus formats. Figure 22.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1)
(b) I2C bus format (Start condition retransmission, FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1)
Figure 22.3 I C Bus Formats
2
SDA
SCL S
1 to 7 SLA
8 R/W
9 A
1 to 7 DATA
2
8
9 A
1 to 7 DATA
8
9 A P
Figure 22.4 I C Bus Timing
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Section 22 I2C Bus Interface 2 (IIC2)
[Legend] S: SLA: R/W: A: DATA: P: 22.4.2 Start condition. The master device drives SDA from high to low while SCL is high. Slave address Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge. The receive device drives SDA to low. Transfer data Stop condition. The master device drives SDA from low to high while SCL is high. Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 22.5 and 22.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 22 I2C Bus Interface 2 (IIC2)
SCL (Master output) SDA (Master output)
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0 R/W
9
1 Bit 7
2 Bit 6
Slave address SDA (Slave output) TDRE TEND ICDRT ICDRS Address + R/W
A
Data 1
Data 2
Address + R/W
Data 1
User processing
[2] Instruction of start condition issuance
[4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte)
Figure 22.5 Master Transmit Mode Operation Timing (1)
SCL (Master output) SDA (Master output) SDA (Slave output) TDRE TEND ICDRT ICDRS Data n A
9
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0
9
A/A
Data n
User [5] Write data to ICDRT processing
[6] Issue stop condition. Clear TEND. [7] Set slave receive mode
Figure 22.6 Master Transmit Mode Operation Timing (2)
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Section 22 I2C Bus Interface 2 (IIC2)
22.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 22.7 and 22.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0 and set the ACKBT bit in ICIER. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 and set the ACKBT bit in ICIER. to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, and clearing the STOP bit in ICSR issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. Clear the MST bit in ICCR1 and then, the operation returns to the slave receive mode.
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Section 22 I2C Bus Interface 2 (IIC2)
Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE TEND TRS RDRF ICDRS ICDRR User processing A 9 1
Master receive mode 2 3 4 5 6 7 8 9 A 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Data 1
Data 1 [3] Read ICDRR [1] Clear TDRE after clearing [2] Read ICDRR (dummy read) TEND and TRS
Figure 22.7 Master Receive Mode Operation Timing (1)
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Section 22 I2C Bus Interface 2 (IIC2)
SCL (Master output) SDA (Master output) SDA (Slave output) RDRF RCVD ICDRS ICDRR User processing
9 A
1
2
3
4
5
6
7
8
9 A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data n-1 Data n-1
Data n Data n
[5] Read ICDRR after setting RCVD
[7] Read ICDRR, and clear RCVD
[6] Issue stop condition [8] Set slave receive mode
Figure 22.8 Master Receive Mode Operation Timing (2) 22.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 22.9 and 22.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by the ACKBT bit in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When the TEND bit is set, clear the TEND bit. 4. Clear the TRS bit for the end processing, and read ICDRR (dummy read). SCL is free. 5. Clear the TDRE bit.
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Section 22 I2C Bus Interface 2 (IIC2)
Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE TEND TRS ICDRT ICDRS ICDRR User processing
Slave transmit mode 9 1 2 3 4 5 6 7 8 9 A 1
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Data 1
Data 2
Data 3
Data 1
Data 2
[2] Write data to ICDRT (data 1)
[2] Write data to ICDRT (data 2)
[2] Write data to ICDRT (data 3)
Figure 22.9 Slave Transmit Mode Operation Timing (1)
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Section 22 I2C Bus Interface 2 (IIC2)
Slave receive mode Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE TEND TRS ICDRT ICDRS ICDRR User processing Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 A 1 2 3 4 5 6 7 8 9 A
Data n
[3] Clear TEND
[4] Read ICDRR (dummy read) [5] Clear TDRE after clearing TRS
Figure 22.10 Slave Transmit Mode Operation Timing (2)
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Section 22 I2C Bus Interface 2 (IIC2)
22.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 22.11 and 22.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) RDRF ICDRS ICDRR User processing A A
9
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0
9
1 Bit 7
Data 1
Data 2 Data 1
[2] Read ICDRR (dummy read)
[2] Read ICDRR
Figure 22.11 Slave Receive Mode Operation Timing (1)
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Section 22 I2C Bus Interface 2 (IIC2)
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) RDRF ICDRS ICDRR User processing
9
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0
9
A
A
Data 1
Data 2 Data 1
[3] Set ACKBT
[3] Read ICDRR [4] Read ICDRR
Figure 22.12 Slave Receive Mode Operation Timing (2) 22.4.6 Clock Synchronous Serial Format
This module can be operated with the clock synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format
Figure 22.13 shows the clock synchronous serial transfer format. The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5 Bit 6
Bit 7
Figure 22.13 Clock Synchronous Serial Transfer Format
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Section 22 I2C Bus Interface 2 (IIC2)
(2)
Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 22.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear the TRS bit while the TDRE bit is 1.
SCL SDA (Output) TRS TDRE ICDRT ICDRS User processing
1 Bit 0
2 Bit 1
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
Data 1 Data 1
Data 2 Data 2
Data 3 Data 3
[3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS
[3] Write data to ICDRT
[3] Write data to ICDRT
Figure 22.14 Transmit Mode Operation Timing
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Section 22 I2C Bus Interface 2 (IIC2)
(3)
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 22.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data.
SCL SDA (Input) MST TRS RDRF ICDRS ICDRR User processing
1 Bit 0
2 Bit 1
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
2 Bit 1
Data 1
Data 2 Data 1
Data 3 Data 2
[2] Set MST (when outputting the clock)
[3] Read ICDRR
[3] Read ICDRR
Figure 22.15 Receive Mode Operation Timing
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Section 22 I2C Bus Interface 2 (IIC2)
22.4.7
Noise Canceller
The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 22.16 shows a block diagram of the noise canceller circuit. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C SCL or SDA input signal D Latch Q D
C Q Latch Match detector Internal SCL or SDA signal
System clock period Sampling clock
Figure 22.16 Block Diagram of Noise Canceller 22.4.8 Example of Use
2
Flowcharts in respective modes that use the I C bus interface are shown in figures 22.17 to 22.20.
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Section 22 I2C Bus Interface 2 (IIC2)
Start Initialize Read BBSY in ICCR2 No [1] BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1. Write 1 to BBSY and 0 to SCP. Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Read ACKBR in ICIER [6] ACKBR=0 ? Yes Transmit mode? Yes No Mater receive mode [12] Clear the STOP flag. [13] Issue the stop condition. [8] TDRE=1 ? Yes No Last byte? [9] Yes Write transmit data in ICDRT Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ICSR Write 0 to BBSY and SCP Read STOP in ICSR No [14] STOP=1 ? Yes Set MST to 0 and TRS to 0 in ICCR1 Clear TDRE in ICSR End [11] [12] [13] [14] Wait for the creation of stop condition. [15] Set slave receive mode. Clear TDRE. No [11] Clear the TEND flag. [8] [9] Wait for ICDRT empty. Set the last byte of transmit data. [3] [2] [3] [4] [4] [5] [6] [7] Issue the start condition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. Set the second and subsequent bytes (except for the final byte) of transmit data. [1] [2] Test the status of the SCL and SDA lines. Set master transmit mode.
[10] Wait for last byte to be transmitted.
Write transmit data in ICDRT Read TDRE in ICSR No
[7]
[15]
Figure 22.17 Sample Flowchart for Master Transmit Mode
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Section 22 I2C Bus Interface 2 (IIC2)
Mater receive mode [1] Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Last receive - 1? No Read ICDRR Yes
[5] [4] [2]
Clear TEND, select master receive mode, and then clear TDRE.* Set acknowledge to the transmit device.* Dummy-read ICDRR.* Wait for 1 byte to be received Check whether it is the (last receive - 1). Read the receive data. Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). Read the (final byte - 1) of receive data. Wait for the last byte to be receive.
[2]
[1]
[3] [4] [5] [6] [7] [8] [9]
[3]
[10] Clear the STOP flag.
[6]
[11] Issue the stop condition. [12] Wait for the creation of stop condition. Set ACKBT in ICIER to 1
[7]
[13] Read the last byte of receive data. [14] Clear RCVD.
Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR No RDRF=1 ? Yes Clear STOP in ICSR. Write 0 to BBSY and SCP Read STOP in ICSR No
[12] [10] [9] [8]
[15] Set slave receive mode.
[11]
STOP=1 ? Yes Read ICDRR
[13] [14]
Clear RCVD in ICCR1 to 0
Clear MST in ICCR1 to 0 End
[15]
Note: When 1 byte is received, skip steps [2] to [6] after [1] and then jump to step [7]. In step [8], dummy-read ICDRR. * Do not activate an interrupt during the execution of steps [1] to [3].
Figure 22.18 Sample Flowchart for Master Receive Mode
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Section 22 I2C Bus Interface 2 (IIC2)
Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] TDRE=1 ? Yes No
Last byte?
[1] Clear the AAS flag. [1] [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag . [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag.
Yes Write transmit data in ICDRT Read TEND in ICSR No
[5] TEND=1 ? Yes Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End
[6] [7] [8] [9]
Figure 22.19 Sample Flowchart for Slave Transmit Mode
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Section 22 I2C Bus Interface 2 (IIC2)
Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR
[1] [2] Set acknowledge to the transmit device. [2] [3] Dummy-read ICDRR. [3] [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). [4] [6] Read the receive data. [7] Set acknowledge of the last byte.
Read RDRF in ICSR No RDRF=1 ? Yes
Last receive - 1?
Yes
[5]
[8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received.
No Read ICDRR
[6] [10] Read for the last byte of receive data.
Set ACKBT in ICIER to 1
[7]
Read ICDRR Read RDRF in ICSR No
[8]
[9]
RDRF=1 ? Yes Read ICDRR End
[10] Note: When 1 byte is received, skip steps [2] to [6] after [1] and then jump to step [7]. In step [8], dummy-read ICDRR.
Figure 22.20 Sample Flowchart for Slave Receive Mode
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Section 22 I2C Bus Interface 2 (IIC2)
22.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun. Table 22.3 shows the contents of each interrupt request. Table 22.3 Interrupt Requests
Clock Synchronous Mode Available Available Available Not available Not available Available
Interrupt Request Transmit data empty Transmit end Receive data full STOP recognition NACK receive Arbitration lost/overrun
Abbreviation TXI TEI RXI STPI NAKI
Interrupt Condition (TDRE=1) * (TIE=1) (TEND=1) * (TEIE=1) (RDRF=1) * (RIE=1) (STOP=1) * (STIE=1) {(NACKF=1)+(AL=1)} * (NAKIE=1)
I C Mode Available Available Available Available Available Available
2
When interrupt conditions described in table 22.3 are 1 and the I bit in CCR is 0, the CPU executes interrupt exception processing. Interrupt sources should be cleared in the exception processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted.
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Section 22 I2C Bus Interface 2 (IIC2)
22.6
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 22.21 shows the timing of the bit synchronous circuit and table 22.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor timing reference clock
SCL
VIH
Internal SCL
Figure 22.21 Timing of Bit Synchronous Circuit Table 22.4 Time for Monitoring SCL
CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc
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Section 22 I2C Bus Interface 2 (IIC2)
22.7
22.7.1
Usage Notes
Note on Issuing Stop Condition and Start (Re-Transmit) Condition
The stop condition or start (re-transmit) condition should be issued after recognizing the falling edge of the ninth clock. The falling edge of the ninth clock can be recognized by checking the 2 SCLO bit in the I C control register 2 (ICCR2). Note that if the stop condition or start (re-transmit) condition is issued in a particular timing and the situations shown below, these conditions may not correctly output. 1. The rising edge of the SCL becomes less sharp and longer due to the SCL bus load (load capacitor and pull-up resistor) than the period defined in section 22.6, Bit Synchronous Circuit. 2. When the slave device elongates the low level period between the eighth and ninth clocks and activates the bit synchronous circuit. 22.7.2 Note on Setting WAIT Bit in I C Bus Mode Register (ICMR)
2 2
The WAIT bit in the I C bus mode register (ICMR) should be set to 0. Note that if the WAIT bit is set to 1, when a slave device holds the SCL signal low more than one transfer clock cycle during the eighth clock, the high level period of the ninth clock may be shorter than a given period. 22.7.3 Restriction on Transfer Rate Setting in Multimaster Operation
In multimaster operation, if the IIC transfer rate setting in this LSI is slower than those of the other masters, SCL may be output with an unexpected width. To avoid this phenomenon, set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest transfer rate of the other masters is set to 400 kbps, the IIC transfer rate in this LSI should be set to 223 kbps (= 400/1.18) or more.
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Section 22 I2C Bus Interface 2 (IIC2)
22.7.4
Restriction on the Use of Bit Manipulation Instructions for MST and TRS Setting in Multimaster Operation
In multimaster operation, if the master transmit is set with bit manipulation instructions in the order from the MST bit to the TRS bit, the AL bit in the ICSR register will be set to 1 but the master transmit mode (MST = 1, TRS = 1) may be set, depending on the arbitration lost timing. To avoid this phenomenon, the following actions should be performed: * In multimaster operation, use the MOV instruction to set bits MST and TRS. * When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than MST = 0 and TRS = 0, set MST = 0 and TRS = 0 again. 22.7.5 Usage Note on Master Receive Mode
In master receive mode, SCL is fixed low on the falling edge of the 8th clock while the RDRF bit is set to 1. When ICDRR is read around the falling edge of the 8th clock, the clock is only fixed low in the 8th clock of the next round of data reception. The SCL is then released from its fixed state without reading ICDRR and the 9th clock is output. As a result, some receive data is lost. To avoid this phenomenon, the following actions should be performed: * Read ICDRR in master receive mode before the rising edge of the 8th clock. * Set RCVD to 1 in master receive mode and perform communication in units of one byte.
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Section 22 I2C Bus Interface 2 (IIC2)
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Section 23 Power-On Reset Circuit
Section 23 Power-On Reset Circuit
This LSI has an on-chip power-on reset circuit. A block diagram of the power-on reset circuit is shown in figure 23.1.
23.1
Feature
* Power-on reset circuit An internal reset signal is generated at turning the power on by externally connecting a capacitor.
Vcc
Vcc Rp RES
CK R
3-bit counter
COUT
R Voltage detector Q S
Internal reset signal
CRES
Figure 23.1 Power-On Reset Circuit
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Section 23 Power-On Reset Circuit
23.2
23.2.1
Operation
Power-On Reset Circuit
The operation timing of the power-on reset circuit is shown in figure 23.2. As the power supply voltage rises, the capacitor, which is externally connected to the RES pin, is gradually charged through the on-chip pull-up resistor (Rp). The low level of the RES pin is sent to the LSI and the whole LSI is reset. When the level of the RES pin reaches to the predetermined level, a voltage detection circuit detects it. Then a 3-bit counter starts counting up. When the 3-bit counter counts for 8 times, an overflow signal is generated and an internal reset signal is negated. The capacitance (CRES) which is connected to the RES pin can be computed using the following formula; where the RES rising time is t. For the on-chip resistor (Rp), see section 26, Electrical Characteristics. The power supply rising time (t_vtr) should be shorter than half the RES rising time (t). The RES rising time (t) is also should be longer than the oscillation stabilization time (trc).
CRES = t Rp (t > trc, t > t_vtr x 2)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur.
t_vtr Vcc
t_vtr x 2 RES V_rst
Internal reset signal
t_cr
t_out (eight states)
Figure 23.2 Power-On Reset Circuit Operation Timing
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Section 24 Address Break
Section 24 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit in CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address. With the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. Use of module standby mode enables this module to be placed in standby mode independently when not used (for details, refer to section 6.4, Module Standby Function). Figure 24.1 shows a block diagram of the address break.
Internal address bus
Comparator
BAR2E Interrupt generation control circuit
BAR2H
BAR2L ABRKCR2 ABRKSR2
BDR2H
BDR2L
Comparator
Interrupt [Legend] BAR2E, BAR2H, BAR2L: BDR2H, BDR2L: ABRKCR2: ABRKSR2: Break address register 2 Break data register 2 Address break control register 2 Address break status register 2
Figure 24.1 Block Diagram of Address Break
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Internal data bus
Section 24 Address Break
24.1
Register Descriptions
The address break has the following registers. * Address break control register 2 (ABRKCR2) * Address break status register 2 (ABRKSR2) * Break address register 2 (BAR2E, BAR2H, BAR2L) * Break data register 2 (BDR2H, BDR2L) 24.1.1 Address Break Control Register 2 (ABRKCR2)
ABRKCR2 sets address break conditions.
Bit 7 Bit Name RTINTE2 Initial Value 1 R/W R/W Description RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 5 CSEL21 CSEL20 0 0 R/W R/W Condition Select 1 and 0 These bits set address break conditions. 00: Instruction execution cycle (no data comparison) 01: CPU data read cycle 10: CPU data write cycle 11: CPU data read/write cycle 4 3 2 ACMP22 ACMP21 ACMP20 0 0 0 R/W R/W R/W Address Compare Condition Select 2 to 0 These bits set the comparison condition between the address set in BAR2 and the internal address bus. 000: Compares all of 24-bit addresses 001: Compares upper 20-bit addresses 010: Compares upper 16-bit addresses 011: Compares upper 12-bit addresses 100: Compares upper 8-bit addresses 101: Compares upper 4-bit addresses 11x: Setting prohibited
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Section 24 Address Break
Bit 1 0
Bit Name DCMP21 DCMP20
Initial Value 0 0
R/W R/W R/W
Description Data Compare Condition Select 1 and 0 These bits set the comparison condition between the data set in BDR2 and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDR2L and data bus 10: Compares upper 8-bit data between BDR2H and data bus 11: Compares 16-bit data between BDR2 and data bus
[Legend] x: Don't care
When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 24.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 25.1, Register Addresses (Address Order). Table 24.1 Access and Data Bus Used
Word Access Even Address ROM space RAM space I/O register with 8-bit data bus width I/O register with 1 16-bit data bus width* I/O register with 2 16-bit data bus width* Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits Odd Address Lower 8 bits Lower 8 bits Upper 8 bits Lower 8 bits Lower 8 bits Byte Access Even Address Upper 8 bits Upper 8 bits Upper 8 bits -- Upper 8 bits Odd Address Upper 8 bits Upper 8 bits Upper 8 bits -- Upper 8 bits
Notes: 1. Registers whose addresses do not range from H'FFFF96 and H'FFFF97, and H'FFFFB8 to H'FFFFBB with 16-bit data bus width. 2. Registers whose addresses range from H'FFFF96 and H'FFFF97, and H'FFFFB8 to H'FFFFBB.
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Section 24 Address Break
24.1.2
Address Break Status Register 2 (ABRKSR2)
ABRKSR2 consists of the address break interrupt flag and the address break interrupt enable bit.
Bit 7 Bit Name ABIF2 Initial Value 0 R/W R/W Description Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR2 is satisfied [Clearing condition] When 0 is written after ABIF2=1 is read 6 ABIE2 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled. 5 to 0 -- All 1 -- Reserved These bits are always read as 1.
24.1.3
Break Address Registers 2 (BAR2E, BAR2H, BAR2L)
BAR2E, BAR2H, and BAR2L are 24-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFFFF. 24.1.4 Break Data Registers 2 (BDR2H, BDR2L)
BDR2H and BDR2L are 16-bit read/write registers that set the data for generating an address break interrupt. BDR2H is compared with the upper 8-bit data bus. BDR2L is compared with the lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for even and odd addresses in the data transmission. Therefore, comparison data must be set in BDR2H for byte access. For word access, the data bus used depends on the address. See section 24.1.1, Address Break Control Register 2 (ABRKCR2), for details. The initial value of this register is undefined.
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Section 24 Address Break
24.2
Operation
When the ABIF2 and ABIE2 bits in ABRKSR2 are set to 1, the address break function generates an interrupt request to the CPU. The ABIF2 bit in ABRKSR2 is set to 1 by the combination of the address set in BAR2, the data set in BDR2, and the conditions set in ABRKCR2. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU. Figures 24.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle Register setting * ABRKCR2 = H'80 * BAR2 = H'00025A Program 000258 * 00025A 00025C 000260 000262 :
NOP * The address break condition is set NOP MOV.W @H'00025A,R0 Underline indicates the address NOP to be stacked. NOP :
NOP NOP MOV MOV instruc- instruc- instruc- instruction tion tion 1 tion 2 Internal prefetch prefetch prefetch prefetch processing Address bus Interrupt request Interrupt acceptance 000258 00025A 00025C 00025E
Stack save
SP-2
SP-4
Figure 24.2 Address Break Interrupt Operation Example (1)
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Section 24 Address Break
When the address break is specified in the data read cycle Register setting * ABRKCR2 = H'A0 * BAR2 = H'00025A Program 000258 00025A * 00025C 000260 000262 :
NOP NOP MOV.W @H'00025A,R0 * The address break condition is set NOP NOP Underline indicates the address : to be stacked.
MOV MOV NOP MOV NOP Next instruc- instruc- instruc- instruc- instrucinstrution 1 tion 2 tion tion tion ction Internal Stack prefetch prefetch prefetch execution prefetch prefetch processing save Address bus Interrupt request Interrupt acceptance 00025C 00025E 000260 00025A 000262 000264 SP-2
Figure 24.2 Address Break Interrupt Operation Example (2)
24.3
Operating States of Address Break
The operating states of the address break are shown in table 24.2. Table 24.2 Operating States of Address Break
Operating Mode
ABRKCR2 ABRKSR2 BAR2E BAR2H BAR2L BDR2H BDR2L
Reset
Reset Reset Reset Reset Reset Retained* Retained*
Active
Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Sleep
Retained Retained Retained Retained Retained Retained Retained
Watch
Retained Retained Retained Retained Retained Retained Retained
Sub-active
Functioning Functioning Functioning Functioning Functioning Functioning Functioning
Sub-sleep Standby
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Module Standby
Retained Retained Retained Retained Retained Retained Retained
Note:
*
Undefined at a power-on reset
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Section 25 List of Registers
Section 25 List of Registers
The register list gives information on the on-chip register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) * Registers are listed from the lower allocation addresses. * Registers are classified by functional modules. * The data bus width is indicated. * The number of access states is indicated. 2. Register bits * Bit configurations of the registers are described in the same order as the register addresses. * Reserved bits are indicated by in the bit name column. * When registers consist of 16 bits, bits are described from the MSB side. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev. 2.00 Jul. 04, 2007 Page 525 of 692 REJ09B0309-0200
Section 25 List of Registers
25.1
Register Addresses (Address Order)
The data bus width indicates the number of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Abbreviation SCR4 SCSR4 TDR4 RDR4 Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Data Bus Access Module Name Width State SCI4 SCI4 SCI4 SCI4 ROM ROM ROM ROM ROM ROM SYSTEM TPU TPU I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Register Name Serial control register 4 Serial control/status register 4 Transmit data register 4 Receive data register 4
Address* H'F00C H'F00D H'F00E H'F00F H'F020 H'F021 H'F022 H'F023 H'F02B H'F02C H'F02F H'F030 H'F031 H'F033 H'F034 H'F037 H'F038 H'F03B H'F03C H'F040 H'F041 H'F042 H'F044 H'F045
1
Flash memory control register 1 FLMCR1 Flash memory control register 2 FLMCR2 Flash memory power control register Erase block register 1 Flash memory enable register Erase block register 2 System control register 3 Timer start register Timer synchro register Port data register E Port data register F Port control register E Port control register F Port mode register E Port mode register F Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 FLPWCR EBR1 FENR EBR2 SYSCR3 TSTR TSYR PDRE PDRF PCRE PCRF PMRE PMRF TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1
Rev. 2.00 Jul. 04, 2007 Page 526 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Name Timer counter_1 Timer general register A_1 Timer general register B_1 PWM3 control register PWM3 data register Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 PWM4 control register PWM4 data register RTC Interrupt flag register Second data register/free running counter data register Minute data register Hour data register Day-of-week data register RTC control register 1 RTC control register 2 SUB32k control register Clock source select register I C bus control register 1 I C bus control register 2 I C bus mode register
2 2 2 2
Abbreviation TCNT_1 TGRA_1 TGRB_1 PWCR3 PWDR3 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 PWCR4 PWDR4 RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 SUB32CR RTCCSR ICCR1 ICCR2 ICMR
Bit No. 16 16 16 8 16 8 8 8 8 8 16 16 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8
Address* H'F046 H'F048 H'F04A H'F04C H'F04E H'F050 H'F051 H'F052 H'F054 H'F055 H'F056 H'F058 H'F05A H'F05D H'F05E H'F067 H'F068 H'F069 H'F06A H'F06B H'F06C H'F06D H'F06E H'F06F H'F078 H'F079 H'F07A H'F07B
1
Data Bus Access Module Name Width State TPU_1 TPU_1 TPU_1 14-bit PWM_3 14-bit PWM_3 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 14-bit PWM_4 14-bit PWM_4 RTC RTC RTC RTC RTC RTC RTC Clock pulse generator RTC IIC2 IIC2 IIC2 IIC2 16 16 16 8 16 8 8 8 8 8 16 16 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
I C bus interrupt enable register ICIER
Rev. 2.00 Jul. 04, 2007 Page 527 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Name I C bus status register Slave address register I C bus transmit data register I C bus receive data register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Serial mode register 3_3 Bit rate register 3_3 Serial control register 3_3 Transmit data register 3_3 Serial status register 3_3 Receive data register 3_3
2 2 2
Abbreviation ICSR SAR ICDRT ICDRR IPRA IPRB IPRC IPRD IPRE IPRF SMR3_3 BRR3_3 SCR3_3 TDR3_3 SSR3_3 RDR3_3
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address* H'F07C H'F07D H'F07E H'F07F H'F080 H'F081 H'F082 H'F083 H'F084 H'F085 H'F088 H'F089 H'F08A H'F08B H'F08C H'F08D H'F096 H'F097 H'F098 H'F099 H'F09A H'F09B H'F09D H'FF84 H'FF85 H'FF86 H'FF8C H'FF8E H'FF90
1
Data Bus Access Module Name Width State IIC2 IIC2 IIC2 IIC2 Interrupts Interrupts Interrupts Interrupts Interrupts Interrupts SCI3_3 SCI3_3 SCI3_3 SCI3_3 SCI3_3 SCI3_3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2
Address break control register 2 ABRKCR2 8 Address break status register 2 ABRKSR2 8 Break address register 2H Break address register 2L Break data register 2H Break data register 2L Break address register 2E Timer mode register G Input capture register GF Input capture register GR Event counter PWM compare register Event counter PWM data register Wakeup edge select register BAR2H BAR2L BDR2H BDR2L BAR2E TMG ICRGF ICRGR ECPWCR ECPWDR WEGR 8 8 8 8 8 8 8 8 16 16 8
Address break 8 Address break 8 Address break 8 Address break 8 Address break 8 Address break 8 Address break 8 Timer G Timer G Timer G AEC* AEC*
2
8 8 8 16 16 8
2
Interrupts
Rev. 2.00 Jul. 04, 2007 Page 528 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Name Serial port control register Input pin edge select register Event counter control register Event counter control/status register Event counter H Event counter L Serial mode register 3_1 Bit rate register 3_1 Serial control register 3_1 Transmit data register 3_1 Serial status register 3_1 Receive data register 3_1 LCD port control register LCD control register LCD control register 2 LCD trimming register BGR control register Serial extended mode register IrDA control register Serial mode register 3_2 Bit rate register 3_2 Serial control register 3_2 Transmit data register 3_2 Serial status register 3_2 Receive data register 3_2 Timer mode register WD Timer control/status register WD1 Timer control/status register WD2
Abbreviation SPCR AEGSR ECCR ECCSR ECH ECL SMR3_1 BRR3_1 SCR3_1 TDR3_1 SSR3_1 RDR3_1 LPCR LCR LCR2 LTRMR BGRMR SEMR IrCR SMR3_2 BRR3_2 SCR3_2 TDR3_2 SSR3_2 RDR3_2 TMWD
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address* H'FF91 H'FF92 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA6 H'FFA7 H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD H'FFB0 H'FFB1 H'FFB2
1
Data Bus Access Module Name Width State SCI3 AEC* AEC* AEC* AEC* AEC*
2 2 2
8 8 8 8 8/16 8/16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
2 2 2 2 2 2 3 3 3 3 3 3 2 2 2 2 2 3 3 3 3 3 3 3 3 2 2 2
2 2
SCI3_1 SCI3_1 SCI3_1 SCI3_1 SCI3_1 SCI3_1 LCD* LCD* LCD* LCD* LCD*
4 4 4 4 4
SCI3_1 IrDA SCI3_2 SCI3_2 SCI3_2 SCI3_2 SCI3_2 SCI3_2 WDT* WDT* WDT*
3 3
TCSRWD1 8 TCSRWD2 8
3
Rev. 2.00 Jul. 04, 2007 Page 529 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Name Timer counter WD Timer mode register C Timer counter C/Timer load register C Timer control register F Timer control/status register F Timer counter FH Timer counter FL Output compare register FH Output compare register FL A/D result register A/D mode register A/D start register Port mode register 1 Oscillator control register Port mode register 3 Port mode register 4 Port mode register 5 Port mode register 9 Port mode register B Port function control register Serial port control register 2 PWM2 control register PWM2 data register PWM1 control register PWM1 data register Port data register 1 Port data register 3 Port data register 4
Abbreviation TCWD TMC TCC/TLC TCRF TCSRF TCFH TCFL OCRFH OCRFL ADRR AMR ADSR PMR1 OSCCR PMR3 PMR4 PMR5 PMR9 PMRB PFCR SPCR2 PWCR2 PWDR2 PWCR1 PWDR1 PDR1 PDR3 PDR4
Bit No. 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 8 8 8
Address* H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC8 H'FFCA H'FFCB H'FFCC H'FFCD H'FFCE H'FFD0 H'FFD2 H'FFD4 H'FFD6 H'FFD7
1
Data Bus Access Module Name Width State WDT*
3
8 8 8 8 8 8/16 8/16 8/16 8/16 16 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 8 8 8
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Timer C Timer C Timer F Timer F Timer F Timer F Timer F Timer F A/D converter A/D converter A/D converter I/O ports Clock pulse generator I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports SCI3 14-bit PWM_2 14-bit PWM_2 14-bit PWM_1 14-bit PWM_1 I/O ports I/O ports I/O ports
Rev. 2.00 Jul. 04, 2007 Page 530 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Name Port data register 5 Port data register 6 Port data register 7 Port data register 8 Port data register 9 Port data register A Port data register B Port data register C Port pull-up control register 1 Port pull-up control register 3 Port pull-up control register 5 Port pull-up control register 6 Port control register 1 Port control register 3 Port control register 4 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register 9 Port control register A Port control register C System control register 1 System control register 2 Interrupt edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt mask register Interrupt request register 1
Abbreviation PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PDRC PUCR1 PUCR3 PUCR5 PUCR6 PCR1 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA PCRC SYSCR1 SYSCR2 IEGR IENR1 IENR2 INTM IRR1
Bit No. 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Address* H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFED H'FFEE H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6
1
Data Bus Access Module Name Width State I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports SYSTEM SYSTEM Interrupts Interrupts Interrupts Interrupts Interrupts 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 2.00 Jul. 04, 2007 Page 531 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Name Interrupt request register 2 Wakeup interrupt request register Clock halt register 1 Clock halt register 2 Clock halt register 3 Notes: 1. 2. 3. 4.
Abbreviation IRR2 IWPR CKSTPR1 CKSTPR2 CKSTPR3
Bit No. 8 8 8 8 8
Address* H'FFF7 H'FFF9 H'FFFA H'FFFB H'FFFC
1
Data Bus Access Module Name Width State Interrupts Interrupts SYSTEM SYSTEM SYSTEM 8 8 8 8 8 2 2 2 2 2
Indicates the lower 16-bit address. AEC: Asynchronous event counter WDT: Watchdog timer LCD: LCD controller/driver
Rev. 2.00 Jul. 04, 2007 Page 532 of 692 REJ09B0309-0200
Section 25 List of Registers
25.2
Register Bits
Register bit names of the on-chip peripheral modules are described below.
Register Abbreviation Bit 7 SCR4 SCSR4 TDR4 RDR4 FLMCR1 FLMCR2 FLPWCR EBR1 FENR EBR2 SYSCR3 TSTR TSYR PDRE PDRF PCRE PCRF PMRE PMRF TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TIE TDRE TDR47 RDR47 FLER PDWND EB7 FLSHE PE7 PCRE7 IOB3 Bit15 Bit7 TGRA_1 Bit15 Bit7 Bit 6 RIE RDRF TDR46 RDR46 SWE EB6 PE6 PCRE6 CCLR1 IOB2 Bit14 Bit6 Bit14 Bit6 Bit 5 TEIE ORER TDR45 RDR45 ESU EB5 PE5 PCRE5 CCLR0 IOB1 Bit13 Bit5 Bit13 Bit5 Bit 4 SOL TEND TDR44 RDR44 PSU EB4 PE4 PCRE4 TMIC CKEG1 IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit 3 SOLP CKS3 TDR43 RDR43 EV EB3 PE3 PF3 PCRE3 PCRF3 IRQ0 CKEG0 IOA3 Bit11 Bit3 Bit11 Bit3 Bit 2 SRES CKS2 TDR42 RDR42 PV EB2 CST2 SYNC2 PE2 PF2 PCRE2 PCRF2 UD IRQ4 TPSC2 IOA2 Bit10 Bit2 Bit10 Bit2 Bit 1 TE CKS1 TDR41 RDR41 E EB1 EB9 CST1 SYNC1 PE1 PF1 PCRE1 PCRF1 IRQ1 NCS TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit 0 RE CKS0 TDR40 RDR40 P EB0 EB8 STS3 PE0 PF0 PCRE0 PCRF0 IRQ3 TMIG TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 TPU_1 I/O ports SYSTEM TPU ROM Module Name SCI4
Rev. 2.00 Jul. 04, 2007 Page 533 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Abbreviation Bit 7 TGRB_1 Bit15 Bit7 PWCR3 PWDR3 PWDR37 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 IOB3 Bit15 Bit7 TGRA_2 Bit15 Bit7 TGRB_2 Bit15 Bit7 PWCR4 PWDR4 PWDR47 RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 SUB32CR FOIFG BSY BSY BSY BSY RUN FOIE Module Name TPU_1
Bit 6 Bit14 Bit6 PWDR36 CCLR1 IOB2 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 PWDR46 WKIFG SC12 MN12 12/24 WKIE
Bit 5 Bit13 Bit5
Bit 4 Bit12 Bit4
Bit 3 Bit11 Bit3
Bit 2 Bit10 Bit2 PWCR32
Bit 1 Bit9 Bit1 PWCR31
Bit 0 Bit8 Bit0 PWCR30 PWDR38 PWDR30 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 PWCR40 PWDR48 PWDR40
14-bit PWM_3
PWDR313 PWDR312 PWDR311 PWDR310 PWDR39 PWDR35 CCLR0 IOB1 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 PWDR34 CKEG1 IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 PWDR33 CKEG0 IOA3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 PWDR32 TPSC2 IOA2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 PWCR42 PWDR31 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 PWCR41
TPU_2
14-bit PWM_4
PWDR413 PWDR412 PWDR411 PWDR410 PWDR49 PWDR45 DYIFG SC11 MN11 HR11 PM DYIE PWDR44 HRIFG SC10 MN10 HR10 RST HRIE PWDR43 MNIFG SC03 MN03 HR03 MNIE PWDR42 SEIFG SC02 MN02 HR02 WK2 1SEIE PWDR41 05SEIFG SC01 MN01 HR01 WK1 05SEIE
025SEIFG RTC SC00 MN00 HR00 WK0 025SEIE Clock pulse generator
32KSTOP
RTCCSR ICCR1 ICCR2
ICE BBSY
RCS6 RCVD SCP
RCS5 MST SDAO
SUB32K TRS SDAOP
RCS3 CKS3 SCLO
RCS2 CKS2
RCS1 CKS1 IICRST
RCS0 CKS0
RTC IIC2
Rev. 2.00 Jul. 04, 2007 Page 534 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Abbreviation Bit 7 ICMR ICIER ICSR SAR ICDRT ICDRR IPRA IPRB IPRC IPRD IPRE IPRF SMR3_3 BRR3_3 SCR3_3 TDR3_3 SSR3_3 RDR3_3 ABRKCR2 ABRKSR2 BAR2H BAR2L BDR2H BDR2L BAR2E TMG ICRGF ICRGR ECPWCR MLS TIE TDRE SVA6 ICDRT7 ICDRR7 IPRA7 IPRB7 IPRC7 IPRD7 IPRE7 IPRF7 COM BRR7 TIE TDR7 TDRE RDR7 RTINTE2 ABIF2 BARH27 BARL27 BDRH27 BDRL27 BARE27 OVFH ICRGF7 ICRGR7 Module Name IIC2
Bit 6 WAIT TEIE TEND SVA5 ICDRT6 ICDRR6 IPRA6 IPRB6 IPRC6 IPRD6 IPRE6 IPRF6 CHR BRR6 RIE TDR6 RDRF RDR6 CSEL21 ABIE2 BARH26 BARL26 BDRH26 BDRL26 BARE26 OVFL ICRGF6 ICRGR6
Bit 5 RIE RDRF SVA4 ICDRT5 ICDRR5 IPRA5 IPRB5 IPRC5 IPRD5 IPRE5 IPRF5 PE BRR5 TE TDR5 OER RDR5 CSEL20 BARH25 BARL25 BDRH25 BDRL25 BARE25 OVIE ICRGF5 ICRGR5
Bit 4 NAKIE NACKF SVA3 ICDRT4 ICDRR4 IPRA4 IPRB4 IPRC4 IPRD4 IPRE4 IPRF4 PM BRR4 RE TDR4 FER RDR4 ACMP22 BARH24 BARL24 BDRH24 BDRL24 BARE24 IIEGS ICRGF4 ICRGR4
Bit 3 BCWP STIE STOP SVA2 ICDRT3 ICDRR3 IPRA3 IPRB3 IPRC3 IPRD3 IPRF3 STOP BRR3 MPIE TDR3 PER RDR3 ACMP21 BARH23 BARL23 BDRH23 BDRL23 BARE23 CCLR1 ICRGF3 ICRGR3
Bit 2 BC2 ACKE AL/OVE SVA1 ICDRT2 ICDRR2 IPRA2 IPRB2 IPRC2 IPRD2 IPRF2 MP BRR2 TEIE TDR2 TEND RDR2 ACMP20 BARH22 BARL22 BDRH22 BDRL22 BARE22 CCLR0 ICRGF2 ICRGR2
Bit 1 BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 IPRA1 IPRB1 IPRC1 IPRD1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 DCMP21 BARH21 BARL21 BDRH21 BDRL21 BARE21 CKS1 ICRGF1 ICRGR1
Bit 0 BC0 ACKBT ADZ FS ICDRT0 ICDRR0 IPRA0 IPRB0 IPRC0 IPRD0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 DCMP20 BARH20 BARL20 BDRH20 BDRL20 BARE20 CKS0 ICRGF0 ICRGR0
Interrupts
SCI3_3
Address break
Timer G
ECPWCR15 ECPWCR14 ECPWCR13 ECPWCR12 ECPWCR11 ECPWCR10 ECPWCR9 ECPWCR8
AEC*1
ECPWCR7 ECPWCR6 ECPWCR5 ECPWCR4 ECPWCR3 ECPWCR2 ECPWCR1 ECPWCR0
Rev. 2.00 Jul. 04, 2007 Page 535 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Abbreviation Bit 7 ECPWDR Module Name AEC*
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9 ECPWDR8
ECPWDR7 ECPWDR6 ECPWDR5 ECPWDR4 ECPWDR3 ECPWDR2 ECPWDR1 ECPWDR0
WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR3_1 BRR3_1 SCR3_1 TDR3_1 SSR3_1 RDR3_1 LPCR LCR LCR2 LTRMR BGRMR SEMR IrCR SMR3_2 BRR3_2 SCR3_2 TDR3_2 SSR3_2 RDR3_2 TMWD TCSRWD1 TCSRWD2
WKEGS7 AHEGS1 ACKH1 OVH ECH7 ECL7 COM BRR7 TIE TDR7 TDRE RDR7 DTS1 LCDAB TRM3
WKEGS6 AHEGS0 ACKH0 OVL ECH6 ECL6 CHR BRR6 RIE TDR6 RDRF RDR6 DTS0 PSW HCKS TRM2
WKEGS5 SPC32 ALEGS1 ACKL1 ECH5 ECL5 PE BRR5 TE TDR5 OER RDR5 CMX ACT CHG TRM1 IrCKS1 PE BRR5 TE TDR5 OER RDR5 B4WI WT/IT
WKEGS4 SPC31 ALEGS0 ACKL0 CH2 ECH4 ECL4 PM BRR4 RE TDR4 FER RDR4 DISP SUPS TRM0 IrCKS0 PM BRR4 RE TDR4 FER RDR4 TCSRWE B3WI
WKEGS3 SCINV3 AIEGS1 PWCK2 CUEH ECH3 ECL3 STOP BRR3 MPIE TDR3 PER RDR3 SGS3 CKS3 ABCS STOP BRR3 MPIE TDR3 PER RDR3 CKS3 B2WI IEOVF
WKEGS2 SCINV2 AIEGS0 PWCK1 CUEL ECH2 ECL2 MP BRR2 TEIE TDR2 TEND RDR2 SGS2 CKS2 CTRM2 BTRM2 MP BRR2 TEIE TDR2 TEND RDR2 CKS2 WDON
WKEGS1 SCINV1
WKEGS0 SCINV0
Interrupts SCI3 AEC*
1
ECPWME PWCK0 CRCH ECH1 ECL1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 SGS1 CKS1 CTRM1 BTRM1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 CKS1 BOWI CRCL ECH0 ECL0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 SGS0 CKS0 CTRM0 BTRM0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 CKS0 WRST
SCI3_1
LCD*3
BGRSTPN IrE COM BRR7 TIE TDR7 TDRE RDR7 B6WI OVF IrCKS2 CHR BRR6 RIE TDR6 RDRF RDR6 TCWE B5WI
SCI3_1 IrDA SCI3_2
WDT*2
Rev. 2.00 Jul. 04, 2007 Page 536 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Abbreviation Bit 7 TCWD TMC TCC/TLC TCW7 TMC7 TCC7/ TLC7 TCRF TCSRF TCFH TCFL OCRFH OCRFL ADRR TOLH OVFH TCFH7 TCFL7 OCRFH7 OCRFL7 ADR9 ADR1 AMR ADSR PMR1 OSCCR ADSF Module Name WDT*2 Timer C
Bit 6 TCW6 TMC6 TCC6/ TLC6 CKSH2 CMFH TCFH6 TCFL6 OCRFH6 OCRFL6 ADR8 ADR0 TRGE LADS RFCUT
Bit 5 TCW5 TMC5 TCC5/ TLC5 CKSH1 OVIEH TCFH5 TCFL5 OCRFH5 OCRFL5 ADR7 CKS1
Bit 4 TCW4 TCC4/ TLC4 CKSH0 CCLRH TCFH4 TCFL4 OCRFH4 OCRFL4 ADR6 CKS0
Bit 3 TCW3 TMC3 TCC3/ TLC3 TOLL OVFL TCFH3 TCFL3 OCRFH3 OCRFL3 ADR5 CH3
Bit 2 TCW2 TMC2 TCC2/ TLC2 CKSL2 CMFL TCFH2 TCFL2 OCRFH2 OCRFL2 ADR4 CH2 IRQAECF
Bit 1 TCW1 TMC1 TCC1/ TLC1 CKSL1 OVIEL TCFH1 TCFL1 OCRFH1 OCRFL1 ADR3 CH1 AEVL OSCF
Bit 0 TCW0 TMC0 TCC0/ TLC0 CKSL0 CCLRL TCFH0 TCFL0 OCRFH0 OCRFL0 ADR2 CH0 AEVH
Timer F
A/D converter
I/O ports Clock pulse generator
PMR3 PMR4 PMR5 PMR9 PMRB PFCR SPCR2 PWCR2 PWDR2
WKP7
WKP6
WKP5
WKP4
WKP3
TMOFH WKP2 IRQ4 IRQ3 PWCR22
TMOFL WKP1 PWM2 IRQ1 SC32S SCINV5 PWCR21
TMOW TMIF WKP0 PWM1 IRQ0 SC31S SCINV4 PWCR20 PWDR28 PWDR20 PWCR10 PWDR18 PWDR10
I/O ports
ADTSTCHG
CLKOUT1 CLKOUT0 PWDR27 PWDR26 PWDR16
PWM4 SPC33
PWM3
SCI3 14-bit PWM_2
PWDR213 PWDR212 PWDR211 PWDR210 PWDR29 PWDR25 PWDR24 PWDR23 PWDR22 PWCR12 PWDR21 PWCR11
PWCR1 PWDR1
PWDR17
14-bit PWM_1
PWDR113 PWDR112 PWDR111 PWDR110 PWDR19 PWDR15 PWDR14 PWDR13 PWDR12 PWDR11
Rev. 2.00 Jul. 04, 2007 Page 537 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Abbreviation Bit 7 PDR1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PDRC PUCR1 PUCR3 PUCR5 PUCR6 PCR1 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA PCRC SYSCR1 SYSCR2 IEGR IENR1 P37 P57 P67 P77 P87 PB7 PC7 PUCR37 PUCR57 PUCR67 PCR37 PCR57 PCR67 PCR77 PCR87 PCRC7 SSBY NMIEG IENRTC Module Name I/O ports
Bit 6 P16 P36 P56 P66 P76 P86 PB6 PC6 PUCR16 PUCR36 PUCR56 PUCR66 PCR16 PCR36 PCR56 PCR66 PCR76 PCR86 PCRC6 STS2 TMIFEG
Bit 5 P15 P55 P65 P75 P85 PB5 PC5 PUCR15 PUCR55 PUCR65 PCR15 PCR55 PCR65 PCR75 PCR85 PCRC5 STS1
Bit 4 P14 P54 P64 P74 P84 PB4 PC4 PUCR14 PUCR54 PUCR64 PCR14 PCR54 PCR64 PCR74 PCR84 PCRC4 STS0 NESEL
Bit 3 P13 P53 P63 P73 P83 P93 PA3 PB3 PC3 PUCR13 PUCR53 PUCR63 PCR13 PCR53 PCR63 PCR73 PCR83 PCR93 PCRA3 PCRC3 LSON DTON IEG3 IEN3
Bit 2 P12 P32 P42 P52 P62 P72 P82 P92 PA2 PB2 PC2 PUCR12 PUCR52 PUCR62 PCR12 PCR32 PCR42 PCR52 PCR62 PCR72 PCR82 PCR92 PCRA2 PCRC2 TMA3 MSON IENEC2
Bit 1 P11 P31 P41 P51 P61 P71 P81 P91 PA1 PB1 PC1 PUCR11 PUCR51 PUCR61 PCR11 PCR31 PCR41 PCR51 PCR61 PCR71 PCR81 PCR91 PCRA1 PCRC1 MA1 SA1 IEG1 IEN1
Bit 0 P10 P30 P40 P50 P60 P70 P80 P90 PA0 PB0 PC0 PUCR10 PUCR30 PUCR50 PUCR60 PCR10 PCR30 PCR40 PCR50 PCR60 PCR70 PCR80 PCR90 PCRA0 PCRC0 MA0 SA0 IEG0 IEN0
SYSTEM
ADTRGNEG IEG4
Interrupts
IENWP
IEN4
Rev. 2.00 Jul. 04, 2007 Page 538 of 692 REJ09B0309-0200
Section 25 List of Registers
Register Abbreviation Bit 7 IENR2 INTM IRR1 IRR2 IWPR CKSTPR1 IENDT IRRDT IWPF7 S4CK STP* CKSTPR2
3
Bit 6 IENAD IRRAD IWPF6 S31CK STP TPUCK STP
Bit 5 IWPF5 S32CK STP
Bit 4 IENTG IRR4 IRRTG IWPF4
Bit 3 IENTFH IRR3 IRRTFH IWPF3
Bit 2 IENTFL IRREC2 IRRTFL IWPF2
Bit 1 IENTC INTM1 IRRI1 IRRTC IWPF1
Bit 0 IENEC INTM0 IRRI0 IRREC IWPF0 RTCCK STP LDCKSTP
Module Name Interrupts
ADCKSTP
TFCKSTP FROMCK STP*
3
SYSTEM
ADBCK STP
IICCKSTP PW2CK STP
AECCK STP PW3CK STP
WDCK STP
PW1CK STP
CKSTPR3
S33CK STP
TCCKSTP TGCKSTP PW4CK STP
Notes: 1. 2. 3. 4.
AEC: Asynchronous event counter WDT: Watchdog timer LCD: LCD controller/driver This bit is available only for the flash memory version. In the masked ROM version, this bit is reserved.
Rev. 2.00 Jul. 04, 2007 Page 539 of 692 REJ09B0309-0200
Section 25 List of Registers
25.3
Register States in Each Operating Mode
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Watch Subactive Subsleep Standby Initialized Initialized Initialized 14-bit PWM_3 TPU_1 I/O ports SYSTEM TPU ROM Module SCR4
Register Abbreviation SCR4 SCSR4 TDR4 RDR4 FLMCR1 FLMCR2 FLPWCR EBR1 FENR EBR2 SYSCR3 TSTR TSYR PDRE PDRF PCRE PCRF PMRE PMRF TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 PWCR3 PWDR3
Rev. 2.00 Jul. 04, 2007 Page 540 of 692 REJ09B0309-0200
Section 25 List of Registers Register Abbreviation TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 PWCR4 PWDR4 RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 SUB32CR
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep
Watch
Subactive Subsleep
Standby
Module TPU_2
14-bit PWM_4 RTC
Clock pulse generator RTC IIC2
RTCCSR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR IPRA IPRB IPRC
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized

Interrupts
Rev. 2.00 Jul. 04, 2007 Page 541 of 692 REJ09B0309-0200
Section 25 List of Registers Register Abbreviation IPRD IPRE IPRF SMR3_3 BRR3_3 SCR3_3 TDR3_3 SSR3_3 RDR3_3 ABRKCR2 ABRKSR2 BAR2H BAR2L BDR2H BDR2L BAR2E TMG ICRGF ICRGR ECPWCR ECPWDR WEGR SPCR AEGSR ECCR ECCSR ECH ECL SMR3_1 BRR3_1 SCR3_1
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep
Watch
Subactive Subsleep
Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Interrupts
Initialized Initialized Initialized Initialized Initialized Initialized
SCI3_3
Address break
Timer G
AEC*1
Interrupts SCI3 AEC*1
Initialized Initialized Initialized
SCI3_1
Rev. 2.00 Jul. 04, 2007 Page 542 of 692 REJ09B0309-0200
Section 25 List of Registers Register Abbreviation TDR3_1 SSR3_1 RDR3_1 LPCR LCR LCR2 LTRMR BGRMR SEMR IrCR SMR3_2 BRR3_2 SCR3_2 TDR3_2 SSR3_2 RDR3_2 TMWD TCSRWD1 TCSRWD2 TCWD TMC TCC/TLC TCRF TCSRF TCFH TCFL OCRFH OCRFL ADRR AMR ADSR
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep
Watch
Subactive Subsleep
Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module SCI3_1
Initialized Initialized Initialized
LCD*3
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCI3_1 IrDA SCI3_2
WDT*2
Timer C
Timer F
A/D converter
Rev. 2.00 Jul. 04, 2007 Page 543 of 692 REJ09B0309-0200
Section 25 List of Registers Register Abbreviation PMR1 OSCCR
Reset Initialized Initialized
Active
Sleep
Watch
Subactive Subsleep
Standby
Module I/O ports Clock pulse generator I/O ports
PMR3 PMR4 PMR5 PMR9 PMRB PFCR SPCR2 PWCR2 PWDR2 PWCR1 PWDR1 PDR1 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PDRC PUCR1 PUCR3 PUCR5 PUCR6 PCR1
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized

SCI3 14-bit PWM_2 14-bit PWM_1 I/O ports
Rev. 2.00 Jul. 04, 2007 Page 544 of 692 REJ09B0309-0200
Section 25 List of Registers Register Abbreviation PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA PCRC SYSCR1 SYSCR2 IEGR IENR1 IENR2 INTM IRR1 IRR2 IWPR CKSTPR1 CKSTPR2 CKSTPR3
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep
Watch
Subactive Subsleep
Standby
Module I/O ports
SYSTEM
Interrupts
SYSTEM
Notes: is not initialized. 1. AEC: Asynchronous event counter 2. WDT: Watchdog timer 3. LCD: LCD controller/driver
Rev. 2.00 Jul. 04, 2007 Page 545 of 692 REJ09B0309-0200
Section 25 List of Registers
Rev. 2.00 Jul. 04, 2007 Page 546 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
Section 26 Electrical Characteristics
26.1 Absolute Maximum Ratings for F-ZTAT Version
Table 26.1 lists the absolute maximum ratings. Table 26.1 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Other than port B Port B Operating temperature Symbol VCC AVCC Vin AVin Topr Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 (general 2 specifications)* -40 to +85 (wide temperature range 2 specifications)* Storage temperature Tstg -55 to +125 C Notes: 1. Permanent damage may occur to the chip if absolute maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. When the operating voltage (Vcc) for reading the flash memory is from 2.7 V to 3.6 V, the operating temperature (Ta) for programming/erasing ranges from -20 to +75C. When the operating voltage (Vcc) for reading the flash memory is from 1.8 V to 3.6 V, the operating temperature (Ta) for programming/erasing ranges from -20 to +50C. Unit V V V V C Note *
1
Rev. 2.00 Jul. 04, 2007 Page 547 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.2
26.2.1
Electrical Characteristics for F-ZTAT Version
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
(1) System clock oscillator selected (10-MHz version)
fW (kHz)
fosc (MHz)
10.0
38.4 32.768
2.0 1.8 2.7 3.6 Vcc (V) 2.7 3.6 Vcc (V) 1.8 * All operating modes * Refer to note
* Active (high-speed) mode * Sleep (high-speed) mode
(2) System clock oscillator selected (4-MHz version)
fW (kHz)
38.4 32.768
fosc (MHz)
4.2 2.0 1.8 2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
2.7 3.6 Vcc (V) 1.8 * All operating modes * Refer to note
Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation stabilization time has elapsed after switching on.
Figure 26.1 Power Supply Voltage and Oscillation Frequency Range (1)
Rev. 2.00 Jul. 04, 2007 Page 548 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
(3) On-chip oscillator for system clock selected Rosc used (reference value)
fW (kHz)
10.0
38.4 32.768
fosc (MHz)
0.5 1.8 2.7 3.6 Vcc (V) 1.8 2.7 3.6 Vcc (V) * All operating modes * Refer to note
* Active (high-speed) mode * Sleep (high-speed) mode
Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation stabilization time has elapsed after switching on.
Figure 26.2 Power Supply Voltage and Oscillation Frequency Range (2)
Rev. 2.00 Jul. 04, 2007 Page 549 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version) 10.0
19.2
SUB (kHz)
(MHz)
16.384 9.6 8.192 4.8
4.2 2.0 4.096
1.8
2.7 3.6 Vcc (V)
1.8
2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode (other than CPU)
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
1250
(kHz)
525
31.25
1.8
2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (other than CPU)
Figure 26.3 Power Supply Voltage and Operating Frequency Range (1)
Rev. 2.00 Jul. 04, 2007 Page 550 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
(2) System clock oscillator selected (4-MHz version)
SUB (kHz)
10.0
19.2 16.384 9.6 8.192
(MHz)
4.2 4.8 2.0 4.096
1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode (other than CPU)
1.8 2.7 3.6 Vcc (V) * Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
1250
525
(kHz)
31.25
1.8
2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (other than CPU)
Figure 26.4 Power Supply Voltage and Operating Frequency Range (2)
Rev. 2.00 Jul. 04, 2007 Page 551 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
(3) On-chip oscillator for system clock selected
19.2
SUB (kHz)
16.384 9.6 8.192 4.8 4.096
Rosc used (reference value)
(MHz)
10.0 0.5 1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode (other than CPU)
1.8 2.7 3.6 Vcc (V) * Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Rosc used (reference value) 1250
(kHz)
7.8125
1.8
2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (other than CPU)
Figure 26.5 Power Supply Voltage and Operating Frequency Range (3)
Rev. 2.00 Jul. 04, 2007 Page 552 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version) 10.0
(MHz)
4.2 2.0 1.8 2.7 3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
(2) System clock oscillator selected (4-MHz version) 10.0
(MHz)
4.2 2.0 1.8 2.7 3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
Figure 26.6 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (1)
(3) On-chip oscillator for system clock selected Rosc used (reference value)
(MHz)
10.0 0.5
1.8
2.7
3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
Figure 26.7 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2)
Rev. 2.00 Jul. 04, 2007 Page 553 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.2.2
DC Characteristics
Table 26.2 lists DC characteristics. Table 26.2 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Test Condition
3
Values Min. Typ. Max. VCC + 0.3 Unit V Note
Item Input high voltage
Symbol VIH
Applicable Pins RES, TEST, NMI* , WKP0 to WKP7, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK33, SCK32, SCK31, SCK4 IRQ0*5, IRQ1*5, IRQ3*5 RXD33, RXD32, RXD31, IrRxD, UD OSC1 X1 P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3, TCLKA, TCLKB, TCLKC, TIOCA1, TIOCA2, TIOCB1, TIOCB2, SCL, SDA PB0 to PB7 IRQAEC
0.9 VCC
0.9 VCC 0.8 VCC 0.9 VCC 0.9 VCC 0.8 VCC
AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3
V V V V V
0.8 VCC 0.9 VCC
AVCC + 0.3 VCC + 0.3
V V
Rev. 2.00 Jul. 04, 2007 Page 554 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. -0.3 Typ. Max. 0.1 VCC Unit V Note
Item Input low voltage
Symbol VIL
Applicable Pins RES, TEST, NMI* , WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK33, SCK32, SCK31, SCK4
3
Test Condition
RXD33, RXD32, RXD31, IrRXD, UD OSC1 X1 P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA3, PB0 to PB7, PC0 to PC7, PE0 to PE7, PF0 to PF3, TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2, SCL, SDA
-0.3 -0.3 -0.3 -0.3

0.2 VCC 0.1 VCC 0.1 VCC 0.2 VCC
V V V V
Rev. 2.00 Jul. 04, 2007 Page 555 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. VCC - 1.0 VCC - 0.3 Typ. Max. Unit V Note
Item Output high voltage
Symbol VOH
Test Applicable Pins Condition P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3 P90 to P93 -IOH = 1.0 mA VCC = 2.7 to 3.6 V -IOH = 0.1 mA
IOH = 1.0mA VCC = 2.7 to 3.6 V IOH = 0.1 mA
VCC - 1.0 VCC - 0.3

0.5 V
Output low VOL voltage
P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3 P90 to P93
IOL = 0.4 mA
IOL = 15 mA VCC=2.7 to 3.6 V IOL = 10 mA VCC = 2.2 to 3.6 V IOL = 8 mA VCC = 1.8 to 3.6 V

1.0 0.5 0.5 0.4
V
SCL, SDA
IOL = 3.0 mA VCC = 2.0 to 3.6 V IOL = 3.0 mA VCC = 1.8 to 3.0 V
V
0.2VCC
Rev. 2.00 Jul. 04, 2007 Page 556 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. Typ. Max. 1.0 Unit A Note
Item
Test Symbol Applicable Pins Condition TEST, NMI* , OSC1, X1, P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3, P90 to P93
3
Input/output IIL leakage current
VIN = 0.5 V to VCC - 0.5 V
PB0 to PB7 Pull-up MOS current -Ip P10 to P16, P30, P36, P37, P50 to P57, P60 to P67 All input pins except power supply pin
VIN = 0.5 V to AVCC - 0.5 V VCC = 3.0 V, VIN = 0 V
30

1.0 180 A
Input CIN capacitance
f = 1 MHz, VIN = 0 V, Ta = 25C
15.0
pF
Rev. 2.00 Jul. 04, 2007 Page 557 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. Typ. 1.1 Max. Unit mA Note Max. guideline = 1.1 x typ *1 *2 *4 Max. guideline = 1.1 x typ *1 *2 Max. guideline = 1.1 x typ *1 *2 *1 *2
Item
Test Symbol Applicable Pins Condition VCC Active (high-speed) mode, VCC = 1.8 V, fOSC = 2 MHz Active (high-speed) mode, VCC = 3.0 V, fOSC = Rosc Active (high-speed) mode, VCC = 3.0 V, fOSC = 4 MHz Active (high-speed) mode, VCC = 3.0 V, fOSC = 10 MHz IOPE2 VCC Active (mediumspeed) mode, VCC = 1.8 V, fOSC = 2 MHz, osc/64 Active (mediumspeed) mode, VCC = 3.0 V, fOSC = 4 MHz, osc/64 Active (mediumspeed) mode, VCC = 3.0 V, fOSC = 10 MHz, osc/64
Active mode IOPE1 supply current
3.7
3.4
7.4
11.0
0.4
mA
Max. guideline = 1.1 x typ *1 *2 *4 Max. guideline = 1.1 x typ *1 *2
0.7
1.1
1.5
*1 *2
Sleep mode ISLEEP supply current
VCC
VCC = 1.8 V, fOSC = 2 MHz VCC = 3.0 V, fOSC = 4 MHz VCC = 3.0 V, fOSC = 10 MHz
1.0
mA
Max. guideline = 1.1 x typ *1 *2 *4 Max. guideline = 1.1 x typ *1 *2 *1 *2

2.5 5.2
7.5
Rev. 2.00 Jul. 04, 2007 Page 558 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. Typ. 9 Max. Unit A Note *1 *2 Reference value
Item
Test Symbol Applicable Pins Condition VCC VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator used (SUB = W/8) VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator used (SUB = W/2)
Subactive ISUB mode supply current
27
50
*1 *2
Subsleep ISUBSP mode supply current
VCC
VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator used (SUB = W/2)
5.5
9.0
A
*1 *2
Watch mode IWATCH supply current
VCC
VCC = 1.8 V, Ta = 25C 32-kHz crystal resonator used VCC = 2.7 V, 32-kHz crystal resonator used
0.5
A
*1 *2 Reference value *1 *2
1.5
5.0
Standby ISTBY mode supply current
VCC
VCC = 3.0 V, Ta = 25C 32-kHz crystal resonator not used 32-kHz crystal resonator not used 1.5
0.1
A
*1 *2 Reference value *1 *2
1.0
5.0 V
RAM data retaining voltage
VRAM
VCC
Rev. 2.00 Jul. 04, 2007 Page 559 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. Vcc = 2.7 to 3.6 V Vcc = 1.8 to 3.6 V Typ. Max. Unit 0.5 15.0 20.0 60.0 2.0 0.2 mA mA mA Note
Item Allowable output low current (per pin) Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total)
Test Symbol Applicable Pins Condition IOL Output pins except port 9 P90 to P93 IOL Output pins except port 9 Port 9 -IOH All output pins
- IOH
All output pins
10.0
mA
Notes: 1. Pin states during current measurement.
Mode Active (high-speed) mode (IOPE1) Active (medium-speed) mode (IOPE2) Sleep mode VCC Only on-chip timers operate On-chip WDT oscillator is off Subactive mode VCC Only CPU operates On-chip WDT oscillator is off Subsleep mode VCC Only on-chip timers operate, CPU stops On-chip WDT oscillator is off Watch mode VCC Only time base operates, CPU stops VCC On-chip WDT oscillator is off Standby mode VCC CPU and timers both stop On-chip WDT oscillator is off 32KSTOP = 1 VCC System clock oscillator: crystal resonator Subclock oscillator: crystal resonator VCC VCC System clock oscillator: crystal resonator Subclock oscillator: crystal resonator VCC RES Pin Internal State VCC Only CPU operates On-chip WDT oscillator is off Other Pins VCC Oscillator Pins System clock oscillator: crystal resonator Subclock oscillator: Pin X1 = GND
Rev. 2.00 Jul. 04, 2007 Page 560 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
2. 3. 4. 5.
Excludes current in pull-up MOS transistors and output buffers. Used for the determination of user mode or boot mode when the reset is released. Only for 4-MHz version. When IRQ0, IRQ1, and IRQ3 in PMRB are set to 0, and IRQ0, IRQ1, and IRQ3 in PMRE are set to 1, the maximum value is VCC + 0.3 (V).
Rev. 2.00 Jul. 04, 2007 Page 561 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.2.3
AC Characteristics
Table 26.3 lists the control signal timing, table 26.4 lists the serial interface timing, and table 26.5 2 lists the I C bus interface timing. Table 26.3 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Symbol Pins fOSC OSC1, OSC2 Values Test Condition VCC = 2.7 to 3.6 V (10-MHz version) VCC = 1.8 to 3.6 V (4-MHz version) On-chip oscillator for system clock selected VCC = 1.8 to 3.0 V OSC1, OSC2 VCC = 2.7 to 3.6 V (10-MHz version) VCC = 1.8 to 3.6 V (4-MHz version) System clock on- tROSC chip oscillation clock (ROSC) cycle time System clock () tcyc cycle time On-chip oscillator for system clock selected VCC = 1.8 to 3.6 V Min. Typ. 2.0 2.0 0.5 -- -- -- Max. 10.0 4.2 10.0 *3 Unit MHz Reference Figure
Item System clock oscillation frequency
System clock on- fRosc chip oscillation frequency OSC clock (OSC) tOSC cycle time
100
--
500
ns
Figure 26.14
238
--
500
100
--
2000
*3
1 --
-- --
64 32
tOSC s
Rev. 2.00 Jul. 04, 2007 Page 562 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Test Condition Min. Typ. -- Max. Unit kHz
Item Subclock oscillation frequency
Applicable Symbol Pins fW X1, X2
Reference Figure
32.768 -- or 38.4 30.5 or -- 26.0 -- -- 20 80 0.8 1.2 -- -- 8 -- 45 -- 2.0 3.0 50 25
Watch clock (W) tW cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation trc stabilization time tsubcyc
X1, X2
-- 2 2
s tW tcyc tsubcyc s
Figure 26.14 *1
OSC1, OSC2
Ceramic resonator -- (Vcc = 2.2 to 3.6 V) Ceramic resonator (other than above) Crystal resonator (VCC = 2.7 to 3.6 V) Crystal resonator (VCC = 2.2 to 3.6 V) Other than above -- -- -- -- --
Figure 26.23
ms
ms s *3
On-chip oscillator for system clock X1, X2
At switching on
VCC = 2.2 to 3.6 V Other than above
-- -- 40 95 --
-- 4 -- -- 15.26 or 13.02
2 -- -- -- --
s
Figure 5.5
External clock high width
tCPH
OSC1
VCC = 2.7 to 3.6 V (10-MHz version) VCC = 1.8 to 3.6 V (4-MHz version)
ns
Figure 26.14
X1
s
Rev. 2.00 Jul. 04, 2007 Page 563 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Test Condition VCC = 2.7 to 3.6 V (10-MHz version) VCC = 1.8 to 3.6 V (4-MHz version) X1 Min. Typ. 40 95 -- -- -- 15.26 or 13.02 -- -- -- -- -- -- -- Max. -- -- -- s Unit ns
Item External clock low width
Applicable Symbol Pins tCPL OSC1
Reference Figure Figure 26.14
External clock rising time
tCPr
OSC1
VCC = 2.7 to 3.6 V (10-MHz version) VCC = 1.8 to 3.6 V (4-MHz version)
-- -- --
10 24 55.0 10 24 55.0 --
ns
Figure 26.14
X1 External clock falling time tCPf OSC1 VCC = 2.7 to 3.6 V (10-MHz version) VCC = 1.8 to 3.6 V (4-MHz version) X1 RES pin low width tREL RES
-- -- -- 10
ns
Figure 26.14
tcyc
Figure 26.15 *2
Rev. 2.00 Jul. 04, 2007 Page 564 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Test Condition Min. Typ. 2 -- Max. -- Unit tcyc tsubcyc
Item Input pin high width
Applicable Symbol Pins tIH IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG AEVL, AEVH
Reference Figure Figure 26.16
VCC = 2.7 to 3.6 V (10-MHz version) VCC = 1.8 to 3.6 V (4-MHz version)
50 110 1.5 2.5
-- -- -- --
-- -- -- --
ns
tTCKWH
TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2 IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG AEVL, AEVH
Single edge specified Both edges specified
tcyc
Figure 26.19
Input pin low width
tIL
2
--
--
tcyc tsubcyc
Figure 26.16
VCC = 2.7 to 3.6 V (10-MHz version) VCC = 1.8 to 3.6 V (4-MHz version)
50 110 1.5 2.5
-- -- -- --
-- -- -- --
ns
tTCKWL
TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2
Single edge specified Both edges specified
tcyc
Figure 26.19
Rev. 2.00 Jul. 04, 2007 Page 565 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Test Condition Min. Typ. 4 -- Max. -- Unit tcyc tsubcyc
Item
Applicable Symbol Pins
Reference Figure Figure 26.21
UD pin minimum UD transition width
Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2. For details on the power-on reset characteristics, refer to table 26.8 and figure 26.18. 3. The specifications may vary due to the effects of temperature, power-supply voltage, and dispersion of product lots. Thorough evaluation under the actual conditions of use is essential in the design of systems. Please confirm with our sales representatives for actual specification.
Table 26.4 Serial Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Values Item Input clock cycle Asynchronous Clock synchronous tSCKW tTXD tRXS VCC = 2.7 to 3.6 V Other than above tRXH VCC = 2.7 to 3.6 V Other than above Symbol Test Condition tscyc Min. 4 6 0.4 -- 100 238 100 238 -- -- ns Typ. -- -- -- -- -- Max. -- -- 0.6 1 -- Unit tcyc or tsubcyc Reference Figure Figure 26.17
Input clock pulse width Transmit data delay time (clock synchronous) Receive data setup time (clock synchronous) Receive data hold time (clock synchronous)
tscyc tcyc or tsubcyc ns
Figure 26.17 Figure 26.18 Figure 26.18 Figure 26.18
Rev. 2.00 Jul. 04, 2007 Page 566 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
Table 26.5 I C Bus Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified.
Test Condition Values Min. 12tcyc + 600 3tcyc + 300 5tcyc + 300 -- -- 5tcyc 3tcyc 3tcyc 3tcyc 1tcyc + 20 0 0 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 300 1tcyc -- -- -- -- -- -- 400 300 Unit ns ns ns ns ns ns ns ns ns ns ns pF ns Reference Figure Figure 26.20
2
Item SCL input cycle time SCL input high width SCL input low width Falling time for SCL and SDA inputs Pulse width of spike on SCL and SDA to be suppressed SDA input bus-free time Start condition input hold time Repeated start condition input setup time Stop condition input setup time Data-input setup time Data-input hold time Capacitive load of SCL and SDA Falling time of SCL and SDA output
Symbol tSCL tSCLH tSCLL tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSf
Rev. 2.00 Jul. 04, 2007 Page 567 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.2.4
A/D Converter Characteristics
Table 26.6 lists the A/D converter characteristics. Table 26.6 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Pins AVCC AN0 to AN7 AVCC AVCC AVCC = 3.0 V Values Test Condition Min. 1.8 -0.3 -- -- Typ. Max. -- -- -- 600 3.6 AVCC + 0.3 1.0 -- Unit Notes V V mA A *2 Reference value *3 *1
Item Analog power supply voltage Analog input voltage Analog power supply current
Symbol AVCC AVIN AIOPE AISTOP1
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Nonlinearity error CAIN RAIN
AVCC AN0 to AN7
-- -- --
-- -- --
5 15.0 10.0
A pF k
-- AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V AVCC = 2.0 to 3.6 V VCC = 2.0 to 3.6 V Other than above -- -- -- -- AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V AVCC = 2.0 to 3.6 V VCC = 2.0 to 3.6 V Other than above -- -- --
-- -- -- -- -- -- -- --
10 3.5 5.5 7.5 0.5 4.0 6.0 8.0
bits LSB
*4 LSB LSB
Quantization error Absolute accuracy
*4
Rev. 2.00 Jul. 04, 2007 Page 568 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Test Condition AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V Min. 12.4 Typ. -- Max. 124 Unit s Notes System clock oscillator selected On-chip oscillator for system clock selected Reference value (fRosc = 4 MHz) System clock oscillator selected On-chip oscillator for system clock selected Reference value (fRosc = 1 MHz)
Item Conversion time
Symbol
Applicable Pins
7.8
15.5
31
s
Other than AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V
29.5
--
124
s
31
62
124
s
Notes: 1. Connect AVCC to VCC when the A/D converter is not used. 2. AISTOP1 is the current flowing through the ladder resistor while the A/D converter is idle. 3. AISTOP2 is the current at a reset, in standby or watch mode while the A/D converter is idle, or in the module standby state. 4. Conversion time is 29.5 s.
Rev. 2.00 Jul. 04, 2007 Page 569 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.2.5
LCD Characteristics
Table 26.7 shows the LCD characteristics. Table 26.7 LCD Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Item Segment driver drop voltage Common driver drop voltage LCD power supply split-resistance LCD display voltage V3 power supply voltage V2 power supply voltage V1 power supply voltage 3-V constant voltage LCD power supply circuit supply current ILCD Vcc Vcc = 2.7 V Booster clock: 32.768 kHz -- VLCD1 V1 Between V1 and VSS -- VLCD2 V2 Between V2 and VSS -- 2.0 (VLCD3 x 2) 3.0 (VLCD3 x 3) 12 -- A Reference value* *
45
Values Test Condition ID = 2 A V1 = 2.7 to 3.6 V ID = 2 A V1 = 2.7 to 3.6 V Between V1 and VSS 1.5 3.0 7.0 M -- -- 0.3 V *
1
Symbol VDS
Pins SEG1 to SEG40
Min. --
Typ. --
Max. 0.6
Unit V
Notes *1
VDC
COM1 to COM4
RLCD
VLCD VLCD3
V1 V3 Between V3 and VSS
2.2 0.9
-- 1.0
3.6 1.1
V V
*2 *3*4
--
V
*3*4
--
V
*3*4
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or common pin. 2. When the LCD display voltage is supplied from an external power source, ensure that the following relationship is maintained: V1 V2 V3 VSS. 3. The value when the LCD power supply split-resistor is separated and 3-V constant voltage power supply circuit is driven. 4. For details on the register (BGRMR) setting range when the voltage of the V3 pin is set to 1.0 V, refer to section 21.3.5, BGR Control Register (BGRMR). 5. Includes the supply current of the band-gap reference circuit (BGR) (operation).
Rev. 2.00 Jul. 04, 2007 Page 570 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.2.6
Power-On Reset Circuit Characteristics
Table 26.8 Power-On Reset Circuit Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications), unless otherwise specified.
Test Symbol Condition V_rst t_vtr t_out Values Min. 0.7VCC Typ. 0.8VCC Max. 0.9VCC Unit V Reference Figure Figure 23.2
Item Reset voltage Power supply rise time Reset count time
The Vcc rise time should be shorter than half the RES rise time. 0.8 0.8 -- -- 4.0 16.0 s s On-chip oscillator for system clock selected (Reference value)
Reset count time On-chip pull-up resistance
t_cr RP Vcc = 3.0 V
Adjustable by the value of the external capacitor of the RES pin. 60 100 -- k Figure 23.1
Rev. 2.00 Jul. 04, 2007 Page 571 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.2.7
Watchdog Timer Characteristics
Table 26.9 Watchdog Timer Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications), unless otherwise specified.
Applicable Pins Test Condition Values Min. 0.2 Typ. 0.4 Max. -- Item s Notes *
Item On-chip watchdog timer oscillator overflow time
Symbol tovf
Note:
*
Indicates the period from the start of counting at 0 to the generation of an internal reset when the counter reaches 255 in the case where the on-chip watchdog timer oscillator is selected.
Rev. 2.00 Jul. 04, 2007 Page 572 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.2.8
Flash Memory Characteristics
Table 26.10 lists the flash memory characteristics. Table 26.10 Flash Memory Characteristics Condition A: AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 3.6 V (operating voltage range in reading), VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing), Ta = -20 to +75C (operating temperature range in programming/erasing: regular specifications, wide-range specifications) Condition B: AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 1.8 V to 3.6 V (operating voltage range in reading), VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing), Ta = -20 to +50C (operating temperature range in programming/erasing: regular specifications)
Values Item Programming time (per 128 bytes)* * * Erasing time (per block)* * *
1 3 6 1 2 4
Symbol tP tE NWEC
Test Condition Min. -- -- 1000* * 100* *
8 12 8 11
Typ. 7 100 10000* 10000* -- -- -- 30 200 10 -- -- --
9
Max. 200 1200 -- -- -- -- -- 32 202 12 -- -- --
Unit ms ms Times
Maximum programming count
9
Data retention time Programming Wait time after setting SWE bit*1 Wait time after setting PSU bit*1 Wait time after setting P bit*1*4
tDRP x y z1 z2 z3 1n6 7 n 1000 Additionalprogramming
10* 1 50 28
10
Years s s s s s s s s
198 8 5 5 4
Wait time after clearing P bit*1 Wait time after clearing PSU bit*1

Wait time after setting PV bit*1
Rev. 2.00 Jul. 04, 2007 Page 573 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Item Programming Wait time after dummy write*1 Wait time after clearing PV bit*1 Wait time after clearing SWE bit*1 Maximum programming count*1*4*5 Erase Wait time after setting SWE bit*1 Wait time after setting ESU bit*1 Wait time after setting E bit*1*6 Wait time after clearing E bit*1 Wait time after clearing ESU bit*1 Symbol N x y z Test Condition Min. 2 2 100 -- 1 100 10 10 10 20 2 4 100 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 1000 -- -- 100 -- -- -- -- -- -- 120 Unit s s s Times s s ms s s s s s s Times
Wait time after setting EV bit*1 Wait time after dummy write*1 Wait time after clearing EV bit*1 Wait time after clearing SWE bit*1 Maximum erasing count*1*6*7 N
Notes: 1. Make the time settings in accordance with the programming/erasing algorithms. 2. The programming time for 128 bytes. (Indicates the total time for which the P bit in the flash memory control register 1 (FLMCR1) is set. The programming-verifying time is not included.) 3. The time required to erase one block. (Indicates the total time for which the E bit in the flash memory control register 1 (FLMCR1) is set. The erasing-verifying time is not included.) 4. Programming time maximum value (tP (max.)) = wait time after setting P bit (z) x maximum programming count (N)
Rev. 2.00 Jul. 04, 2007 Page 574 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
5. Set the maximum programming count (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (tP (max.)). The wait time after setting P bit (z1, z2) should be changed as follows according to the value of the programming count (n). Programming count (n) 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Erasing time maximum value (tE (max.)) = wait time after setting E bit (z) x maximum erasing count (N) 7. Set the maximum erasing count (N) according to the actual set value of (z), so that it does not exceed the erasing time maximum value (tE (max.)). 8. The minimum number of times in which all characteristics are guaranteed following reprogramming. (The guarantee covers the range from 1 to the minimum value.) 9. Reference value at 25C. (Guideline showing programming count over which functioning will be retained under normal circumstances.) 10. Data retention characteristics within the range indicated in the specifications, including the minimum programming count. 11. Applies to an operating voltage range when reading data of 2.7 to 3.6 V. 12. Applies to an operating voltage range when reading data of 1.8 to 3.6 V.
26.3
Absolute Maximum Ratings for Masked ROM Version
Table 26.11 lists the absolute maximum ratings. Table 26.11 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Other than port B Port B Operating temperature Symbol VCC AVCC Vin AVin Topr Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 (regular specifications) -40 to +85 (wide-range specifications) Storage temperature Tstg -55 to +125 C Unit V V V V C Note *
Note:
*
Permanent damage may occur to the chip if absolute maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability.
Rev. 2.00 Jul. 04, 2007 Page 575 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.4
26.4.1
Electrical Characteristics for Masked ROM Version
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
(1) System clock oscillator selected 10.0
fosc (MHz)
4.2 2.0 1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode (other than CPU)
Figure 26.8 Power Supply Voltage and Oscillation Frequency Range (1)
(2) On-chip oscillator for system clock selected Rosc used (reference value)
fW (kHz)
38.4 32.768
fosc (MHz)
10.0 0.5 1.8 2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 3.6 Vcc (V) * All operating modes * Refer to note
Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation stabilization time has elapsed after switching on.
Figure 26.9 Power Supply Voltage and Oscillation Frequency Range (2)
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Section 26 Electrical Characteristics
(1) System clock oscillator selected 10.0
19.2
SUB (kHz)
(MHz)
16.384 9.6 8.192 4.8
4.2 2.0 4.096
1.8
2.7 3.6 Vcc (V)
1.8
2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode (other than CPU)
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
1250
525
(kHz)
31.25
1.8
2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode (other than CPU)
Figure 26.10 Power Supply Voltage and Operating Frequency Range (1)
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Section 26 Electrical Characteristics
(2) On-chip oscillator for system clock selected
SUB (kHz)
19.2 16.384 9.6 8.192
Rosc used (reference value)
(MHz)
10.0 4.8 0.5 4.096
1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode Rosc used (reference value)
1.8 2.7 3.6 Vcc (V) * Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
(kHz)
1250
7.8125
1.8
2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode
Figure 26.11 Power Supply Voltage and Operating Frequency Range (2)
(1) System clock oscillator selected 10.0
(MHz)
4.2 2.0 1.8 2.7 3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
Figure 26.12 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (1)
Rev. 2.00 Jul. 04, 2007 Page 578 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
(2) On-chip oscillator for system clock selected Rosc used (reference value)
(MHz)
10.0 0.5
1.8
2.7
3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
Figure 26.13 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2)
Rev. 2.00 Jul. 04, 2007 Page 579 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.4.2
DC Characteristics
Table 26.12 lists the DC characteristics. Table 26.12 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Test Condition Values Min. Typ. Max. VCC + 0.3 Unit V Note
Item Input high voltage
Symbol Applicable Pins VIH RES, TEST, NMI, WKP0 to WKP7, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK33, SCK32, SCK31 IRQ04, IRQ14, IRQ34 RXD33, RXD32, RXD31, IrRXD, UD OSC1 X1 P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3, TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2, SCL, SDA PB0 to PB7 IRQAEC
0.9 VCC --
0.9 VCC -- 0.8 VCC -- 0.9 VCC -- 0.9 VCC -- 0.8 VCC --
AVCC + 0.3 V VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 V V V V
0.8VCC 0.9VCC
-- --
AVCC + 0.3 V VCC + 0.3 V
Rev. 2.00 Jul. 04, 2007 Page 580 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. -0.3 -- 0.1VCC Unit V Note
Item Input low voltage
Symbol Applicable Pins VIL RES, TEST, NMI, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK33, SCK32, SCK31 RXD33, RXD32, RXD31, IrRXD, UD OSC1 X1 P10 to P16, P30 to P32 P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P93, PA0 to PA3, PB0 to PB7, PC0 to PC7, PE0 to PE7, PF0 to PF3, TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2, SCL, SDA
Test Condition
-0.3 -0.3 -0.3 -0.3
-- -- -- --
0.2VCC 0.1VCC 0.1VCC 0.2VCC
V V V V
Rev. 2.00 Jul. 04, 2007 Page 581 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. VCC - 1.0 -- VCC - 0.3 -- -- -- Unit V Note
Item Output high voltage
Symbol Applicable Pins VOH P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3 P90 to P93
Test Condition -IOH = 1.0 mA VCC = 2.7 to 3.6V -IOH = 0.1 mA
-IOH = 1.0 mA VCC = 2.7 to 3.6V -IOH = 0.1 mA
VCC - 1.0 -- VCC - 0.3 -- -- --
-- -- 0.5 V
Output low VOL voltage
P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3 P90 to P93
IOL = 0.4 mA
IOL = 15 mA VCC = 2.7 to 3.6V IOL = 10 mA VCC = 2.2 to 3.6V IOL = 8 mA VCC = 1.8 to 3.6V
-- -- -- -- --
-- -- -- -- --
1.0 0.5 0.5 0.4 0.2 VCC
V
SCL, SDA
IOL = 3.0 mA VCC = 2.0 to 3.6V IOL = 3.0 mA VCC = 1.8 to 2.0V
V
Rev. 2.00 Jul. 04, 2007 Page 582 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. -- -- 1.0 Unit A Note
Item
Symbol
Applicable Pins TEST, NMI, OSC1, X1, P10 to P16, P30 to P32, P36, P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, IRQAEC, PA0 to PA3, PC0 to PC7, PE0 to PE7, PF0 to PF3, P90 to P93 PB0 to PB7
Test Condition VIN = 0.5 V to VCC - 0.5 V
Input/output | IIL | leakage current
VIN = 0.5 V to AVCC - 0.5 V VCC = 3 V, VIN = 0 V
-- 30
-- --
1.0 180 A
Pull-up MOS current
-Ip
P10 to P16, P30, P36, P37, P50 to P57, P60 to P67 All input pins except power supply pin
Input CIN capacitance
f = 1 MHz, VIN = 0 V, Ta = 25C
--
--
15.0
pF
Rev. 2.00 Jul. 04, 2007 Page 583 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. -- 0.7 -- Unit Note mA Max. guideline = 1.1 x typ.*1 *2 Max. guideline = 1.1 x typ.*1 *2 Max. guideline = 1.1 x typ.*1 *2 *1 *2
Item
Symbol Applicable Pins VCC
Test Condition Active (high-speed) mode, VCC = 1.8 V, fOSC = 2 MHz Active (high-speed) mode, VCC = 3.0 V, fOSC = ROSC Active (high-speed) mode, VCC = 3.0 V, fOSC = 4 MHz Active (high-speed) mode, VCC = 3.0 V, fOSC = 10 MHz
Active mode IOPE1 supply current
--
2.2
--
--
2.6
--
--
6.0
9.0
IOPE2
VCC
Active (mediumspeed) mode, VCC = 1.8 V, fOSC = 2 MHz, osc/64 Active (mediumspeed) mode, VCC = 3.0 V, fOSC = 4 MHz, osc/64
--
0.1
--
mA
Max. guideline = 1.1 x typ.*1 *2
--
0.4
--
Max. guideline = 1.1 x typ.*1 *2
-- Active (mediumspeed) mode, VCC = 3.0 V, fOSC = 10 MHz, osc/64 Sleep mode ISLEEP supply current VCC VCC = 1.8 V, fOSC = 2 MHz VCC = 3.0 V, fOSC = 4 MHz VCC = 3.0 V, fOSC = 10 MHz -- -- --
0.6
0.8
*1 *2
0.3 1.2 2.5
-- -- 4.0
mA
Max. guideline = 1.1 x typ.*1 *2 Max. guideline = 1.1 x typ.*1 *2 *1 *2
Rev. 2.00 Jul. 04, 2007 Page 584 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. -- 6.5 -- Unit Note A Reference value *1 *2
Item
Test Symbol Applicable Pins Condition VCC VCC = 1.8 V, LCD lighting, 32-kHz crystal resonator (SUB = W/2) VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator (SUB = W/8) VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator (SUB = W/2)
Subactive ISUB mode supply current
--
5.5
--
Reference value *1 *2
--
11
17
*1 *2
Subsleep ISUBSP mode supply current
VCC
VCC = 2.7 V, LCD lighting, 32-kHz crystal resonator used (SUB = W/2)
--
5.0
8.5
A
*1 *2
Watch mode IWATCH supply current
VCC
VCC = 1.8 V, Ta = 25C -- 32-kHz crystal resonator used, LCD not used VCC = 2.7 V, 32-kHz crystal resonator used, LCD not used --
0.5
--
A
*1 *2
1.5
5.0
Reference value *1 *2
Standby ISTBY mode supply current
VCC
VCC = 3.0 V, Ta = 25C, 32-kHz crystal resonator not used 32-kHz crystal resonator not used
--
0.1
--
A
Reference value *1 *2
--
1.0
5.0
*1 *2
Rev. 2.00 Jul. 04, 2007 Page 585 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. 1.5 -- -- Unit Note V
Item RAM data retaining voltage Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total)
Test Symbol Applicable Pins Condition VRAM VCC
IOL
Output pins except port 9 P90 to P93
-- -- -- -- Vcc = 2.7 to 3.6 V Vcc = 1.8 to 3.6 V -- --
-- -- -- -- -- --
0.5 15.0 20.0 60.0 2.0 0.2
mA
IOL
Output pins except port 9 Port 9
mA
-IOH
All output pins
mA
- IOH
All output pins
--
--
10.0
mA
Notes: 1. Pin states during current measurement.
Mode Active (high-speed) mode (IOPE1) Active (medium-speed) mode (IOPE2) Sleep mode VCC Only on-chip timers operate On-chip WDT oscillator is off Subactive mode VCC Only CPU operates On-chip WDT oscillator is off Subsleep mode VCC Only on-chip timers operate, CPU stops On-chip WDT oscillator is off Watch mode VCC Only time base operates, CPU stops On-chip WDT oscillator is off VCC VCC VCC System clock oscillator: Crystal resonator Subclock oscillator: Crystal resonator VCC RES Pin VCC Internal State Only CPU operates On-chip WDT oscillator is off Other Pins VCC Oscillator Pins System clock oscillator: Crystal resonator Subclock oscillator: Pin X1 = GND
Rev. 2.00 Jul. 04, 2007 Page 586 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
RES Pin VCC
Mode Standby mode
Internal State CPU and timers both stop On-chip WDT oscillator is off 32KSTOP = 1
Other Pins VCC
Oscillator Pins System clock oscillator: Crystal resonator Subclock oscillator: Crystal resonator
2. Excludes current in pull-up MOS transistors and output buffers. 3. When IRQ0, IRQ1, and IRQ3 in PMRB are set to 0, and IRQ0, IRQ1, and IRQ3 in PMRE are set to 1, the maximum value is VCC + 0.3 (V).
Rev. 2.00 Jul. 04, 2007 Page 587 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.4.3
AC Characteristics
Table 26.13 lists the control signal timing, table 26.14 lists the serial interface timing, and table 2 26.15 lists the I C bus interface timing. Table 26.13 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Symbol Pins fOSC Values Test Condition Min. 2.0 2.0 0.5 Typ. -- -- -- Max. 10.0 4.2 10.0 *3 Unit MHz Reference Figure
Item System clock oscillation frequency
OSC1, OSC2 VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V On-chip oscillator for system clock selected VCC = 1.8 to 3.6 V OSC1, OSC2 VCC = 2.7 to 3.6 V
System clock on- fRosc chip oscillation frequency OSC clock (OSC) tOSC cycle time
100
--
500
ns
Figure 26.14
VCC = 1.8 to 3.6 V
238
--
500
System clock on- tROSC chip oscillation clock (ROSC) cycle time System clock () tcyc cycle time
On-chip oscillator for system clock selected VCC = 1.8 to 3.6 V
100
--
2000
*3
1 --
-- --
64 32
tOSC s
Rev. 2.00 Jul. 04, 2007 Page 588 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Test Condition Min. -- Typ. Max. Unit kHz
Item Subclock oscillator oscillation frequency
Applicable Symbol Pins fW X1, X2
Reference Figure
32.768 -- or 38.4
Watch clock (W) tW cycle time Subclock (SUB) cycle time Instruction cycle time Oscillation trc stabilization time tsubcyc
X1, X2
-- 2 2
30.5 or -- 26.0 -- -- 20 80 0.8 1.2 -- -- 8 -- 45 -- 2.0 3.0 50 25
s tW tcyc tsubcyc s
Figure 26.14 *1
OSC1, OSC2 Ceramic resonator -- (Vcc = 2.2 to 3.6 V) Ceramic resonator -- (Other than above) Crystal resonator -- (Vcc = 2.7 to 3.6 V) Crystal resonator -- (Vcc = 2.2 to 3.6 V) Other than above On-chip oscillator for system clock X1, X2 At switching on -- --
Figure 26.23
ms
ms s *3
VCC = 2.2 to 3.6V Other than above
-- -- 40 95 --
-- 4 -- -- 15.26 or 13.02
2 -- -- -- --
s
Figure 5.5
External clock high width
tCPH
OSC1
VCC = 2.7 to 3.6 V VCC = 1.8 to 3.6 V
ns
Figure 26.14
X1
s
Rev. 2.00 Jul. 04, 2007 Page 589 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Item External clock low width Symbol Applicable Pins Test Condition tCPL OSC1 Min. Typ. -- -- 15.26 or 13.02 -- -- -- -- -- -- -- -- Max. -- -- -- s Unit ns
Reference Figure Figure 26.14
VCC = 2.7 to 3.6 V 40 VCC = 1.8 to 3.6 V 95
X1
--
External clock rising time
tCPr
OSC1
VCC = 2.7 to 3.6 V -- VCC = 1.8 to 3.6 V --
10 24 55.0 10 24 55.0 -- --
ns
Figure 26.14
X1 External clock falling time tCPf OSC1
-- VCC = 2.7 to 3.6 V -- VCC = 1.8 to 3.6 V --
ns ns Figure 26.14
X1 RES pin low width Input pin high width tREL tIH RES IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG AEVL, AEVH
-- 10 2
ns tcyc tcyc tsubcyc Figure 26.15*2 Figure 26.16
VCC = 2.7 to 3.6 V 50 VCC = 1.8 to 3.6 V 110
-- -- -- --
-- -- -- --
ns
tTCKWH
TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2
Single edge specified Both edges specified
1.5 2.5
tcyc
Figure 26.19
Rev. 2.00 Jul. 04, 2007 Page 590 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Test Condition Min. 2 Typ. -- Max. -- Unit tcyc tsubcyc
Item Input pin low width
Applicable Symbol Pins tIL IRQ0, IRQ1, NMI, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG AEVL, AEVH
Reference Figure Figure 26.16
VCC = 2.7 to 3.6 V 50 VCC = 1.8 to 3.6 V 110
-- -- -- --
-- -- -- --
ns
tTCKWL
TCLKA, TCLKB, TCLKC, TIOCA1, TIOCB1, TIOCA2, TIOCB2
Single edge specified Both edges specified
1.5 2.5
tcyc
Figure 26.19
UD pin minimum UD transition width
4
--
--
tcyc tsubcyc
Figure 24.21
Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2. For details on the power-on reset characteristics, refer to table 26.18 and figure 26.15. 3. The specifications may vary due to the effects of temperature, power-supply voltage, and dispersion of product lots. Thorough evaluation under the actual conditions of use is essential in the design of systems. As for actual specification, please confirm with our sales representatives.
Rev. 2.00 Jul. 04, 2007 Page 591 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
Table 26.14 Serial Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values Item Input clock cycl Asynchronous Clock synchronous Input clock pulse width Transmit data delay time (clock synchronous) Receive data setup time (clock synchronous) Receive data hold time (clock synchronous) tSCKW tTXD tRXS VCC = 2.7 to 3.6 V Other than above tRXH VCC = 2.7 to 3.6 V Other than above Symbol Test Condition tscyc Min. 4 6 0.4 -- 100 238 100 238 -- -- ns Typ. -- -- -- -- -- Max. -- -- 0.6 1 -- Unit tcyc or tsubcyc Reference Figure Figure 26.17
tscyc tcyc or tsubcyc ns
Figure 26.17 Figure 26.18 Figure 26.18 Figure 26.18
Rev. 2.00 Jul. 04, 2007 Page 592 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
Table 26.15 I C Bus Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified.
Values Item SCL input cycle time SCL input high width SCL input low width SCL and SDA input fall time SCL and SDA input spike pulse removal time SDA input bus-free time Start condition input hold time Retransmission start condition input setup time Setup time for stop condition input Data-input setup time Data-input hold time Capacitive load of SCL and SDA SCL and SDA output fall time Symbol Test Condition Min. tSCL tSCLH tSCLL tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSf 12tcyc + 600 3tcyc + 300 5tcyc + 300 -- -- 5tcyc 3tcyc 3tcyc 3tcyc 1tcyc + 20 0 0 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 300 1tcyc -- -- -- -- -- -- 400 300 Unit ns ns ns ns ns ns ns ns ns ns ns pF ns Reference Figure Figure 26.20
2
Rev. 2.00 Jul. 04, 2007 Page 593 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.4.4
A/D Converter Characteristics
Table 26.16 lists the A/D converter characteristics. Table 26.16 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Symbol Pins Test Condition AVCC AVIN AIOPE AISTOP1 AVCC AN0 to AN7 AVCC AVCC AVCC = 3.0 V Values Min. 1.8 -0.3 -- -- Typ. -- -- -- 600 Max. 3.6 Unit V Note *1
Item Analog power supply voltage Analog input voltage Analog power supply current
AVCC + 0.3 V 1.0 -- mA A *2 Reference value *3
AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Nonlinearity error CAIN RAIN
AVCC AN0 to AN7
-- -- --
-- -- --
5 15.0 10.0
A pF k
-- AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V AVCC = 2.0 to 3.6 V VCC = 2.0 to 3.6 V Other than above -- -- -- -- AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V AVCC = 2.0 to 3.6 V VCC = 2.0 to 3.6 V Other than above -- -- --
-- -- -- -- -- -- -- --
10 3.5 5.5 7.5 0.5 4.0 6.0 8.0
bits LSB
*4 LSB LSB
Quantization error Absolute accuracy
*4
Rev. 2.00 Jul. 04, 2007 Page 594 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics Values Min. 12.4 Typ. -- Max. 124 Unit s Note System clock oscillator selected On-chip oscillator for system clock selected Reference value (fRosc = 4 MHz) System clock oscillator selected On-chip oscillator for system clock selected Reference value (fRosc = 1MHz)
Item Conversion time
Applicable Symbol Pins Test Condition AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V
7.8
15.5
31
s
Other than AVCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V
29.5
--
124
s
31
62
124
s
Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at a reset, in standby or watch mode while the A/D converter is idle, or in the module standby state. 4. Conversion time is 29.5 s. Ta = -20 to +75C
Rev. 2.00 Jul. 04, 2007 Page 595 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.4.5
LCD Characteristics
Table 26.17 shows the LCD characteristics. Table 26.17 LCD Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, unless otherwise specified.
Applicable Item Segment driver drop voltage Common driver drop voltage LCD power supply split- RLCD resistance LCD display voltage V3 power supply voltage V2 power supply voltage V1 power supply voltage 3-V constant voltage LCD power supply circuit supply current ILCD Vcc VCC = 2.7 V Booster clock: 32.768 kHz -- VLCD1 V1 Between V1 and VSS -- VLCD2 V2 Between V2 and VSS -- 2.0 (VLCD3 x 2) 3.0 (VLCD3 x 3) 12 -- A Reference value* *
45
Values Test Condition ID = 2 A V1 = 2.7 V to 3.6 V ID = 2 A V1 = 2.7 V to 3.6 V Between V1 and VSS 1.5 3.0 7.0 M -- -- 0.3 V *
1
Symbol VDS
Pins SEG1 to SEG40
Min. Typ. -- --
Max. Unit 0.6 V
Notes *1
VDC
COM1 to COM4
VLCD VLCD3
V1 V3 Between V3 and VSS
2.2 0.9
-- 1.0
3.6 1.1
V V
*2 *3*4
--
V
*3*4
--
V
*3*4
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or common pin. 2. When the LCD display voltage is supplied from an external power source, ensure that the following relationship is maintained: V1 V2 V3 VSS. 3. The value when the LCD power supply split-resistor is separated and 3-V constant voltage power supply circuit is driven. 4. For details on the register (BGRMR) setting range when the voltage of the V3 pin is set to 1.0 V, refer to section 21.3.5, BGR Control Register (BGRMR). 5. Includes the supply current of the band-gap reference circuit (BGR) (operation).
Rev. 2.00 Jul. 04, 2007 Page 596 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.4.6
Power-On Reset Circuit Characteristics
Table 26.18 Power-On Reset Circuit Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20 to +75C (general specifications), Ta = -40 to +85C (wide temperature range specifications), unless otherwise specified.
Test Symbol Condition V_rst t_vtr t_out Values Min. 0.7VCC Typ. 0.8VCC Max. 0.9VCC Unit V Reference Figure Figure 23.2
Item Reset voltage Power supply rise time Reset count time
The Vcc rise time should be shorter than half the RES rise time. 0.8 0.8 -- -- 4.0 16.0 s s On-chip oscillator for system clock selected (Reference value)
Count start time On-chip pull-up resistance
t_cr RP
Adjustable by the value of the external capacitor of the RES pin. Vcc = 3.0 V 60 100 -- k Figure 23.1
26.4.7
Watchdog Timer Characteristics
Table 26.19 Watchdog Timer Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications), unless otherwise specified.
Applicable Pins Test Condition Values Min. 0.2 Typ. 0.4 Max. -- Unit s Note *
Item On-chip watchdog timer oscillator overflow time
Symbol tovf
Note:
*
Indicates the period from the start of counting at 0 to the generation of an internal reset when the counter reaches 255 in the case where the on-chip watchdog timer oscillator is selected.
Rev. 2.00 Jul. 04, 2007 Page 597 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.5
Operation Timing
Figures 26.14 to 26.21 show operation timings.
tOSC, tW
V IH OSC1 X1 V IL t CPH t CPr t CPL t CPf
Figure 26.14 Clock Input Timing
RES
V IL
t REL
Figure 26.15 RES Low Width Timing
NMI, IRQ0, IRQ1, IRQ3, IRQ4, TMIC, TMIF, TMIG, ADTRG, WKP0 to WKP7, IRQAEC, AEVL, AEVH t
IL
V V
IH
IL
t
IH
Figure 26.16 Input Timing
Rev. 2.00 Jul. 04, 2007 Page 598 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
t SCKW
SCK31 SCK32 SCK33 t scyc
Figure 26.17 SCK3 Input Clock Timing
t scyc SCK31 VIH or VOH* SCK32 SCK33 V or V * IL OL t TXD
TXD31 TXD32 TXD33 (transmit data)
VOH* VOL* t RXS t RXH
RXD31 RXD32 RXD33 (receive data) Note: * Output timing reference levels Output high Output low VOH = 1/2 Vcc + 0.2 V VOL = 0.8 V
See figure 26.22 for load conditions.
Figure 26.18 SCI3 Input/Output Timing in Clock Synchronous Mode
Rev. 2.00 Jul. 04, 2007 Page 599 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
TCLKA to TCLKC
tTCKWL
tTCKWH
Figure 26.19 Clock Input Timing for TCLKA to TCLKC Pins
SDA tBUF
VIH VIL tSTAH tSCLH tSTAS tSP tSTOS
SCL P* S* tSf tSCLL tSCL Sr* tSr tSDAH tSDAS P*
Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition
Figure 26.20 I C Bus Interface Input/Output Timing
VIH UD VIL tUDL tUDH
2
Figure 26.21 UD Pin Minimum Transition Width Timing
Rev. 2.00 Jul. 04, 2007 Page 600 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.6
Output Load Circuit
VCC
2.4 k
LSI output pin
30 pF
12 k
Figure 26.22 Output Load Condition
Rev. 2.00 Jul. 04, 2007 Page 601 of 692 REJ09B0309-0200
Section 26 Electrical Characteristics
26.7
Recommended Resonators
(1) Recommended Crystal Resonators Frequency (MHz) Manufacturer NIHON DEMPA KOGYO CO.,LTD. NIHON DEMPA KOGYO CO.,LTD. Product Type
4.194304 10
NR-18 NR-18
(2) Recommended Ceramic Resonators Frequency (MHz) 2 Manufacturer Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Murata Manufacturing Co., Ltd. Product Type CSTCC2M00G53-B0
4.19 10
CSTCC2M00G56-B0 CSTLS4M19G53-B0 CSTLS4M19G56-B0 CSTLS10M0G53-B0 CSTLS10M0G56-B0
Figure 26.23 Recommended Resonators
26.8
Usage Note
The F-ZTAT and masked ROM versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the F-ZTAT version, the same evaluation testing should also be conducted for the masked ROM version when changing over to that version. Connecting a bypass capacitor is recommended for noise suppression.
Rev. 2.00 Jul. 04, 2007 Page 602 of 692 REJ09B0309-0200
Appendix
Appendix
A.
A.1
Instruction Set
Instruction List
Condition Code
Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Logical exclusive OR of the operands on both sides
Rev. 2.00 Jul. 04, 2007 Page 603 of 692 REJ09B0309-0200
Appendix
Symbol ( ), < >
Description NOT (logical complement) Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7).
Condition Code Notation (cont)
Symbol
Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes
* 0 1 --
Rev. 2.00 Jul. 04, 2007 Page 604 of 692 REJ09B0309-0200
Appendix
Table A.1
Instruction Set
1. Data Transfer Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd
B B B B B B
2 2 2 4 8 2
---- ---- ---- ---- ---- ----
#xx:8 Rd8 Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 @ERs Rd8 ERs32+1 ERs32 2 4 6 2 4 8 2 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) ERd32-1 ERd32 Rs8 @ERd 2 4 6 Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16 2 2 4 8 2 Rs16 Rd16 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 @ERs Rd16 ERs32+2 @ERd32 4 6 2 4 8 @aa:16 Rd16 @aa:24 Rd16 Rs16 @ERd Rs16 @(d:16, ERd) Rs16 @(d:24, ERd)
0-- 0-- 0-- 0-- 0-- 0--
2 2 4 6 10 6
MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd
B B B B B B B
---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0--
4 6 8 4 6 10 6
MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd
B B B W4 W W
---- ---- ---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
4 6 8 4 2 4 6 10 6
MOV.W @(d:16, ERs), Rd W MOV.W @(d:24, ERs), Rd W MOV.W @ERs+, Rd W
MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd
W W W
---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0--
6 8 4 6 10
MOV.W Rs, @(d:16, ERd) W MOV.W Rs, @(d:24, ERd) W
Rev. 2.00 Jul. 04, 2007 Page 605 of 692 REJ09B0309-0200
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd
W
2
ERd32-2 ERd32 Rs16 @ERd 4 6 Rs16 @aa:16 Rs16 @aa:24 #xx:32 Rd32 ERs32 ERd32
----
0--
6
W W L L L L L L 6 2 4 6 10 4
---- ---- ---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
6 8 6 2 8 10 14 10
@ERs ERd32 @(d:16, ERs) ERd32 @(d:24, ERs) ERd32 @ERs ERd32 ERs32+4 ERs32 6 8 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd 6 10 4 ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) ERd32-4 ERd32 ERs32 @ERd 6 8 ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP 2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP 4 Cannot be used in this LSI Cannot be used in this LSI
MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd
L L L L L L 4
---- ---- ---- ---- ---- ----
0-- 0-- 0-- 0-- 0-- 0--
10 12 8 10 14 10
MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP POP.W Rn POP.L ERn
L L W
---- ---- ----
0-- 0-- 0--
10 12 6
L
----
0--
10
PUSH PUSH.W Rn PUSH.L ERn
W
----
0--
6
L
----
0--
10
MOVFPE
MOVFPE @aa:16, Rd
B
Cannot be used in this LSI Cannot be used in this LSI
MOVTPE
MOVTPE Rs, @aa:16
B
4
Rev. 2.00 Jul. 04, 2007 Page 606 of 692 REJ09B0309-0200
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
2. Arithmetic Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd
B B
2 2
-- --
Rd8+#xx:8 Rd8 Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16 2 Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32 2 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8 2 2 2 2 2 2 2 2 2 2 Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16 ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16 2 Rd16-Rs16 Rd16
2 2 4 2 6
W4 W L 6
-- (1) -- (1) -- (2)
ADD.L ERs, ERd
L
-- (2)
2
ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC INC.B Rd INC.W #1, Rd INC.W #2, Rd INC.L #1, ERd INC.L #2, ERd DAA SUB DAA Rd
B B L L L B W W L L B
2
-- --
(3) (3)
2 2 2 2 2 2 2 2 2 2 2
------------ ------------ ------------
---- ---- ---- ---- ---- --* --
-- -- -- -- --
*
SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd
B W4 W L L B B L L L B W W 2 6
2
2 4 2 6 2 2 2 2 2 2 2 2 2
-- (1) -- (1)
ERd32-#xx:32 ERd32 -- (2) 2 ERd32-ERs32 ERd32 -- (2)
SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd
Rd8-#xx:8-C Rd8 2 2 2 2 2 2 2 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16
-- --
(3) (3)
------------ ------------ ------------
---- ---- ----
-- -- --
Rev. 2.00 Jul. 04, 2007 Page 607 of 692 REJ09B0309-0200
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
DEC DEC.L #1, ERd DEC.L #2, ERd DAS DAS.Rd
L L B
2 2 2
---- ---- --*
ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8 Rd8 x Rs8 Rd16 (unsigned multiplication) Rd16 x Rs16 ERd32 (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division) Rd8-#xx:8
-- --
2 2 2
*--
MULXU MULXU. B Rs, Rd
B
2
------------
14
MULXU. W Rs, ERd
W
2
------------

22
MULXS MULXS. B Rs, Rd
B
4
----
----
16
MULXS. W Rs, ERd
W
4
----
----
24
DIVXU DIVXU. B Rs, Rd
B
2
-- -- (6) (7) -- --
14
DIVXU. W Rs, ERd
W
2
-- -- (6) (7) -- --
22
DIVXS DIVXS. B Rs, Rd
B
4
-- -- (8) (7) -- --
16
DIVXS. W Rs, ERd
W
4
-- -- (8) (7) -- --
24

CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd
B B
2 2
-- --
2 2 4 2 4 2
Rd8-Rs8 Rd16-#xx:16
W4 W L L 6 2 2
-- (1) -- (1) -- (2) -- (2)
Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32
Rev. 2.00 Jul. 04, 2007 Page 608 of 692 REJ09B0309-0200
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C

NEG NEG.B Rd NEG.W Rd NEG.L ERd EXTU EXTU.W Rd EXTU.L ERd
B W L W
2 2 2 2
-- -- --
0-Rd8 Rd8 0-Rd16 Rd16 0-ERd32 ERd32 0 ( of Rd16) 0 ( of ERd32) ( of Rd16) ( of Rd16) ( of ERd32) ( of ERd32)
2 2 2 2
---- 0
0--
L
2
---- 0
0--
2
EXTS EXTS.W Rd EXTS.L ERd
W
2
----
0--
2
L
2
----
0--
2
Rev. 2.00 Jul. 04, 2007 Page 609 of 692 REJ09B0309-0200
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
3. Logic Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
AND
AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd
B B
2 2
---- ---- ---- ----
Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 2 Rd16Rs16 Rd16
0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0--
2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2
W4 W L L B B W4 W L L B B W4 W L L B W L 6 4 2 2 2 2 2 2 6 4 2 2 2 6 4
ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
OR
OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd
XOR
XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd
ERd32#xx:32 ERd32 -- -- ERd32ERs32 ERd32 -- -- Rd8 Rd8 Rd16 Rd16 Rd32 Rd32 ---- ---- ----
NOT
NOT.B Rd NOT.W Rd NOT.L ERd
Rev. 2.00 Jul. 04, 2007 Page 610 of 692 REJ09B0309-0200
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
4. Shift Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd
ROTXL ROTXL.B Rd
B W L B W L B W L B W L B W L B W L B W L B W L
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C MSB LSB C MSB C MSB 0 MSB C MSB LSB C MSB C MSB LSB LSB LSB LSB LSB
0
---- ---- ---- ---- ---- ---- ----
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
---- ---- ----
C
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
ROTXL.W Rd ROTXL.L ERd
ROTXR ROTXR.B Rd
ROTXR.W Rd ROTXR.L ERd ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd
C MSB LSB
---- ----
Rev. 2.00 Jul. 04, 2007 Page 611 of 692 REJ09B0309-0200
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
5. Bit-Manipulation Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT BNOT #xx:3, Rd
B B B B B B B B B B B B B
2 4 4 2 4 4 2 4 4 2 4 4 2
(#xx:3 of Rd8) 1 (#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8) 4 (#xx:3 of @ERd) (#xx:3 of @ERd) 4 (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) 4 (Rn8 of @ERd) (Rn8 of @ERd) 4 (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z 4 4 (#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z 4 4 (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C
------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
2 8 8 2 8 8 2 8 8 2 8 8 2
BNOT #xx:3, @ERd
B
------------
8
BNOT #xx:3, @aa:8
B
------------
8
BNOT Rn, Rd
B
2
------------
2
BNOT Rn, @ERd
B
------------
8
BNOT Rn, @aa:8
B
------------
8
BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD BLD #xx:3, Rd
B B B B B B B
2
------ ------ ------ ------ ------ ------
---- ---- ---- ---- ---- ----
2 6 6 2 6 6 2
2
2
----------
Rev. 2.00 Jul. 04, 2007 Page 612 of 692 REJ09B0309-0200
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
I
H
N
Z
V
C
BLD
BLD #xx:3, @ERd BLD #xx:3, @aa:8
B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 2 2 2 2 2 2 2 2
4 4
---------- ---------- ---------- ---------- ----------
(#xx:3 of @ERd) C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd) C 4 (#xx:3 of @aa:8) C C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd24) 4 C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C
6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6
BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8
4
------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ----------
4
4
4
4 4
C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C ---------- ---------- ---------- ---------- ----------
4
4 4
C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C 4 C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C ---------- ---------- ---------- ---------- ----------
4
4 4
C (#xx:3 of @ERd24) C -- -- -- -- -- C (#xx:3 of @aa:8) C ----------
Rev. 2.00 Jul. 04, 2007 Page 613 of 692 REJ09B0309-0200
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
6. Branching Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+ Operand Size
Condition Code
No. of States*1
@(d, ERn)
Branch Condition If condition Always is true then PC PC+d Never else next; C Z = 0
I
H
N
Z
V
C
Bcc
BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
------------ ------------ ------------ ------------ ------------ ------------
4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6
C Z = 1
------------ ------------
C=0
------------ ------------
C=1
------------ ------------
Z=0
------------ ------------
Z=1
------------ ------------
V=0
------------ ------------
V=1
------------ ------------
N=0
------------ ------------
N=1
------------ ------------
NV = 0
------------ ------------
NV = 1
------------ ------------
Z (NV) = 0 -- -- -- -- -- -- ------------ Z (NV) = 1 -- -- -- -- -- -- ------------
Rev. 2.00 Jul. 04, 2007 Page 614 of 692 REJ09B0309-0200
Advanced
Mnemonic
Operation
@(d, PC) Normal @@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
JMP
JMP @ERn JMP @aa:24 JMP @@aa:8
-- -- -- --
2 4 2 2
PC ERn PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC ERn 4 PC @-SP PC aa:24 2 PC @-SP PC @aa:8 2 PC @SP+
------------ ------------ ------------ ------------ 8 6
4 6 10 8
BSR
BSR d:8
BSR d:16 JSR
--
4
------------
8
10
JSR @ERn
--
2
------------
6
JSR @aa:24
--
------------
8
10
JSR @@aa:8
--
------------
8
12
RTS
RTS
--
------------
8
10
Rev. 2.00 Jul. 04, 2007 Page 615 of 692 REJ09B0309-0200
Advanced
8
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
7. System Control Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C

RTE
RTE
--
CCR @SP+ PC @SP+ Transition to powerdown state
10
SLEEP SLEEP
-- 2 2 4 6 10 4
2

LDC
LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR
B B W W W W
#xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR @ERs CCR ERs32+2 ERs32 6 8 2 4 6 10 4 @aa:16 CCR @aa:24 CCR CCR Rd8 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) ERd32-2 ERd32 CCR @ERd 6 8 CCR @aa:16 CCR @aa:24
2 2 6 8 12 8

LDC @aa:16, CCR LDC @aa:24, CCR STC STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd
W W B W W W W
8 10 2 6 8 12 8
STC CCR, @aa:16 STC CCR, @aa:24 ANDC ANDC #xx:8, CCR ORC NOP ORC #xx:8, CCR XORC XORC #xx:8, CCR NOP
W W B B B -- 2 2 2
8 10

CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2
2 2 2 2
Rev. 2.00 Jul. 04, 2007 Page 616 of 692 REJ09B0309-0200
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
8. Block Transfer Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
Condition Code
@(d, ERn)
I
H
N
Z
V
C
EEPMOV
EEPMOV. B
--
4 if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next 4 if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next
-- -- -- -- -- -- 8+ 4n*2
EEPMOV. W
--
-- -- -- -- -- -- 8+ 4n*2
Notes: 1. The number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. For other cases, see appendix A.3, Number of Execution States. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev. 2.00 Jul. 04, 2007 Page 617 of 692 REJ09B0309-0200
Advanced
Mnemonic
@-ERn/@ERn+
Operand Size
Operation
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
A.2
Appendix
Table A.2
Instruction code: Instruction when most significant bit of BH is 1.
4 ORC ANDC ADD SUB Table A-2 Table A-2 (2) (2) CMP SUBX MOV ADDX AND.B Table A-2 (2) LDC OR.B XOR.B XORC Table A-2 Table A-2 (2) (2) 5 6 7 8 9 A B C D E F Table A-2 (2) Table A-2 (2)
REJ09B0309-0200
1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0.
3 LDC
AL
AH
0
1
2
0
NOP
Table A-2 (2)
STC
Operation Code Map
1
Table A-2 Table A-2 Table A-2 Table A-2 (2) (2) (2) (2)
2 MOV.B
Rev. 2.00 Jul. 04, 2007 Page 618 of 692
Operation Code Map (1)
3 BLS BNE BVC BVS JMP MOV MOV BIOR BILD ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND Table A-2 Table A-2 EEPMOV (2) (2) Table A-2 (3) Table A-2 (2) BPL BMI RTE BST OR AND BAND BIST BLD BTST BOR BXOR XOR TRAPA BEQ DIVXU RTS BSR BCC BCS BGE BSR BLT BGT JSR BLE
4
BRA
BRN
BHI
5
MULXU
DIVXU
MULXU
6
BSET
BNOT
BCLR
7
8
9
A
B
C
D
E
F
Table A.2
Instruction code:
1st byte 2nd byte AH AL BH BL
3 LDC/STC ADD INC ADDS MOV SHLL SHAL SHAR ROTL ROTR EXTU EXTU NEG SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG SUB DEC DEC SUB CMP BLS BCC OR OR XOR XOR SUB SUB BCS BNE AND AND BEQ BVC BVS BPL BMI BGE BLT BGT BLE DEC DEC EXTS EXTS INC INC INC SLEEP Table A-2 Table A-2 (3) (3) 4 5 6 7 8 9 A B C D E F Table A-2 (3)
BH AH AL
0
1
2
01
MOV
0A
INC
0B
ADDS
Operation Code Map (2)
0F
DAA
10
SHLL
11
SHLR
12
ROTXL
13
ROTXR
17
NOT
1A
DEC
1B
SUBS
1F
DAS
58
BRA
BRN
BHI
79
MOV
ADD
CMP
Rev. 2.00 Jul. 04, 2007 Page 619 of 692
REJ09B0309-0200
7A
MOV
ADD
CMP
Appendix
Appendix
Table A.2
Instruction code: Instruction when most significant bit of DH is 1.
REJ09B0309-0200
1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL Instruction when most significant bit of DH is 0.
CL 3 4 5 6 7 8 9 A B C D E F
AH ALBH BLCH LDC STC STC LDC LDC STC
0
1
2
01406
LDC STC
Rev. 2.00 Jul. 04, 2007 Page 620 of 692
Operation Code Map (3)
01C05 DIVXS OR AND BTST BOR BTST BIOR BIST BIXOR BIAND BILD BST BXOR BAND BLD XOR
MULXS
MULXS
01D05
DIVXS
01F06
7Cr06 * 1
7Cr07 * 1
7Dr06 * 1
BSET
BNOT
BCLR
7Dr07 * 1 BTST BOR BTST BIOR BIXOR BIAND BILD BST BIST BXOR BAND BLD
BSET
BNOT
BCLR
7Eaa6 * 2
7Eaa7 * 2
7Faa6 * 2
BSET
BNOT
BCLR
7Faa7 * 2
BSET
BNOT
BCLR
Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression:
Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8
L=M=N=0
Rev. 2.00 Jul. 04, 2007 Page 621 of 692 REJ09B0309-0200
Appendix
Table A.3
Number of Cycles in Each Instruction
Access Location On-Chip Memory SI SJ SK SL SM SN 2 or 3* -- 1 2 On-Chip Peripheral Module --
Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: *
Depends on which on-chip peripheral module is accessed. See section 25.1, Register Addresses (Address Order).
Rev. 2.00 Jul. 04, 2007 Page 622 of 692 REJ09B0309-0200
Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction Fetch I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDX ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8
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Appendix
Instruction Fetch I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic Bcc BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8
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Appendix
Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 1 2 2 2 2 1 1 2 2 2 2 2 1 1 2 2 2 2 1 1 1 1 2 2 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR BSR d:8 BSR d:16 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8
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Appendix
Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 2n+2*1 2n+2*1 12 20 12 20 1 1 1 1 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DUVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd
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Appendix
Instruction Fetch I 1 1 1 2 2 2 2 2 2 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 2 1 1 1 1 1 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR LDC@(d:24,ERs), CCR LDC@ERs+, CCR LDC@aa:16, CCR LDC@aa:24, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @Erd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8
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Appendix
Instruction Fetch I 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4
2
Instruction Mnemonic MOV MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16,ERd) MOV.W Rs, @(d:24,ERd) MOV MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16,ERs), ERd MOV.L @(d:24,ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs,@ERd MOV.L ERs, @(d:16,ERd) MOV.L ERs, @(d:24,ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 MOVFPE MOVTPE MOVFPE @aa:16, Rd* MOVTPE Rs,@aa:16*2
Branch Stack Addr. Read Operation J K
Byte Data Access L 1 1
Word Data Access M
Internal Operation N
1 1 1 1 1 1 1 1 1 1 1 1 2 2
2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2
2 2
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Appendix
Instruction Fetch I 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N 12 20 12 20
Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC POP ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd
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Appendix
Instruction Fetch I 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 5 2 3 4 1 2 1 3 1 1 1 1 1 1 1 1 2 2 1 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC SLEEP STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16,ERd) STC CCR, @(d:24,ERd) STC CCR,@-ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS SUBS #1/2/4, ERd
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Appendix
Instruction Fetch I 1 1 1 1 2 1 3 2 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR
Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1 times respectively. 2. It cannot be used in this LSI.
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Appendix
A.4
Combinations of Instructions and Addressing Modes Combinations of Instructions and Addressing Modes
Addressing Mode
@ERn+/@ERn @(d:16.ERn) @(d:24.ERn) @(d:16.PC)
Table A.5
@@aa:8
Functions
Instructions
@ERn #xx
@(d:8.PC)
@aa:16
@aa:24
@aa:8
Rn
Data MOV transfer POP, PUSH instructions MOVFPE, MOVTPE Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS Logical AND, OR, XOR operations NOT Shift operations Bit manipulations Branching BCC, BSR instructions JMP, JSR RTS System RTE control SLEEP instructions LDC STC ANDC, ORC, XORC NOP Block data transfer instructions
BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- BWL BWL WL BWL B B -- L -- BWL -- -- B BW -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
B -- -- -- -- -- -- -- -- --
BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- WL -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- B -- B -- --
BWL WL BWL BWL BWL B -- -- -- -- -- B B -- -- --
-- -- -- -- -- B -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- B -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
-- --
BW
Rev. 2.00 Jul. 04, 2007 Page 632 of 692 REJ09B0309-0200
--
Appendix
B.
B.1
I/O Ports
I/O Port Block Diagrams
SBY (Low at a reset or in standby mode)
PUCR1 (PUCR16)
VCC VCC
P16
PDR1 (P16) PCR1 (PCR16)
VSS
Internal data bus
SCI4 module
SCK4 output SCK4 input SCK4 input enable SCK4 output enable
PDR1: PCR1:
Port data register 1 Port control register 1
PUCR1: Port pull-up control register 1
Figure B.1 (a) Port 1 Block Diagram (P16) (F-ZTAT
TM
Version)
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Appendix
SBY
PUCR1 (PUCR16)
VCC VCC
P16
PCR1 (PCR16)
VSS
PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1
Figure B.1 (b) Port 1 Block Diagram (P16) (Masked ROM Version)
SBY
PUCR1 (PUCR1n)
TPU module TIOCA1 output enable (P12) TIOCB1 output enable (P13) TIOCA2 output enable (P14) TIOCB2 output enable (P15)
VCC VCC
Internal data bus
P1n
PDR1 (P1n) PCR1 (PCR1n)
TIOCA1 output (P12) TIOCB1 output (P13) TIOCA2 output (P14) TIOCB2 output (P15) TIOCA1 input (P12) TIOCB1 input (P13) TIOCA2 input (P14) TIOCB2 input (P15)
VSS
Port data register 1 PDR1: Port control register 1 PCR1: PUCR1: Port pull-up control register 1 n = 5 to 2
TCLKA input (P12) TCLKB input (P13) TCLKC input (P14)
Figure B.1 (c) Port 1 Block Diagram (P15 to P12)
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Internal data bus
PDR1 (P16)
Appendix
SBY
PUCR1 (PUCR1n)
VCC VCC
PMR1 (AEVL, AEVH) PDR1 (P1n)
P1n
VSS
PCR1 (PCR1n)
Internal data bus
AEC module AEVH input (P10) AEVL input (P11)
PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 1, 0
Figure B.1 (d) Port 1 Block Diagram (P11, P10)
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Appendix
SBY
PUCR3 (PUCR37)
VCC VCC
Internal data bus
P37
PDR3 (P37) PCR3 (PCR37)
VSS
SCI4 module
SO4 output SO4 output enable
PDR3: PCR3:
Port data register 3 Port control register 3
PUCR3: Port pull-up control register 3
Figure B.2 (a) Port 3 Block Diagram (P37) (F-ZTAT
SBY
TM
Version)
VCC VCC
PUCR3 (PUCR37)
P37
PCR3 (PCR37)
VSS
PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3
Figure B.2 (b) Port 3 Block Diagram (P37) (Masked ROM Version)
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Internal data bus
PDR3 (P37)
Appendix
SBY
PUCR3 (PUCR36)
VCC VCC
Internal data bus
P36
PDR3 (P36) PCR3 (PCR36)
VSS
SCI4 module
SI4 input SI4 input enable
PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3
Figure B.2 (c) Port 3 Block Diagram (P36) (F-ZTAT
SBY
TM
Version)
VCC VCC
PUCR3 (PUCR36)
P36
PCR3 (PCR36)
VSS
PDR3: PCR3:
Port data register 3 Port control register 3
PUCR3: Port pull-up control register 3
Figure B.2 (d) Port 3 Block Diagram (P36) (Masked ROM Version)
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Internal data bus
PDR3 (P36)
Appendix
SBY
PFCR (SC32S)
SPCR (SPC32)
SCI3_2 module
TXD32 output
Internal data bus
VCC
SPCR (SCINV3) PDR3 (P32)
P32
PCR3 (PCR32)
VSS
IIC bus 2 module
IIC2 input/output enable SCL output SCL input
VSS
PDR3: PCR3: SPCR: PFCR :
Port data register 3 Port control register 3 Serial port control register Port function control register
Figure B.2 (e) Port 3 Block Diagram (P32)
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Appendix
SBY
SCI3_2 module
VCC
PFCR (SC32S) PDR3 (P31) PCR3 (PCR31)
RXD32 input enable RXD32 input
VSS
VSS
SPCR (SCINV2)
Internal data bus
P31
I2C bus 2 module
PDR3: PCR3: SPCR: PFCR :
Port data register 3 Port control register 3 Serial port control register Port function control register
IIC input/output enable SDA output SDA input
Figure B.2 (f) Port 3 Block Diagram (P31)
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Appendix
SBY
PUCR (PUCR30)
VCC VCC
PMR3 (TMOW)
RTC module
TMOW output
P30
PDR3 (P30)
VSS
PCR3 (PCR30)
PFCR (SC32S)
Internal data bus
SCI3_2 module
SCK32 input enable SCK32 output enable SCK32 output SCK32 input
PFCR (CLKOUT1)
PFCR (CLKOUT0)
PDR3: PCR3: PMR3: PFCR :
Port data register 3 Port control register 3 Port mode register 3 Port function control register
CLKOUT output OSC, OSC/2, OSC/4
PUCR3: Port pull-up control register 3
Figure B.2 (g) Port 3 Block Diagram (P30)
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Appendix
SBY PFCR (SC31S) SPCR (SCINV1) VCC SPCR (SPC31)
Timer F module TMOFH output
SCI3_1 module TXD31/IrTXD output
P42
PDR4 (P42)
PCR4 (PCR42)
VSS
PMR4 (TMOFH)
PDR4: PCR4: PMR4: SPCR: PFCR:
Port data register 4 Port contol register 4 Port mode register 4 Serial port control register Port function control register
Figure B.3 (a) Port 4 Block Diagram (P42)
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Internal data bus
Appendix
SBY
PFCR (SC31S)
SCI3_1 module
VCC
PMR4 (TMOFL)
RXD31/IrRXD input enable RXD31/IrRXD input
P41
PDR4 (P41)
PCR4 (PCR41)
VSS
Internal data bus
Timer F module
TMOFL output
PDR4: PCR4: PMR4: SPCR: PFCR:
Port data register 4 Port contol register 4 Port mode register 4 Serial port control register Port function control register
SPCR (SCINV0)
Figure B.3 (b) Port 4 Block Diagram (P41)
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Appendix
SBY
PFCR (SC31S)
SCI3_1 module
VCC
SCK31 input enable SCK31 output enable SCK31 output SCK31 input
P40
PCR4 (PCR40)
VSS
PMR4 (TMIF)
Internal data bus
PDR4 (P40)
Timer F nodule
TMIF input PDR4: PCR4: PMR4: PFCR: Port data register 4 Port control register 4 Port mode register 4 Port function control register
Figure B.3 (c) Port 4 Block Diagram (P40)
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Appendix
SBY
PUCR5 (PUCR5n)
VCC VCC
PMR5 (WKPn) PDR5 (P5n) PCR5 (PCR5n)
P5n
VSS
Internal data bus
WKPn input
PDR5: PCR5: PMR5: n = 7 to 0
Port data register 5 Port control register 5 Port mode register 5
PUCR5: Port pull-up control register 5
Figure B.4 Port 5 Block Diagram
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Appendix
SBY
PUCR6 (PUCR6n)
VCC VCC
PCR6 (PCR6n) P6n
VSS
PDR6: PCR6: n = 7 to 0
Port data register 6 Port control register6
PUCR6: Port pull-up control register 6
Figure B.5 Port 6 Block Diagram
SBY
VCC
PCR7 (PCR7n) P7n
VSS
PDR7: PCR7: n = 7 to 0
Port data register 7 Port control register 7
Figure B.6 Port 7 Block Diagram
Rev. 2.00 Jul. 04, 2007 Page 645 of 692 REJ09B0309-0200
Internal data bus
PDR7 (P7n)
Internal data bus
PDR6 (P6n)
Appendix
SBY
VCC
PCR8 (PCR8n) P8n
VSS
PDR8: PCR8: n = 7 to 0
Port data register 8 Port control register 8
Figure B.7 Port 8 Block Diagram
PWM module
PWM4 output SBY
PFCR (PWM4)
VCC
PCR9 (PCR93) P93
VSS
PDR9: PCR9: PFCR:
Port data register 9 Port contol register 9 Port function control register
Figure B.8 (a) Port 9 Block Diagram (P93)
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Internal data bus
PDR9 (P93)
Internal data bus
PDR8 (P8n)
Appendix
PWM module
PWM3 output SBY
PFCR (PWM3)
VCC
PMR9 (IRQ4) PDR9 (P92) PCR9 (PCR92)
P92
VSS
Internal data bus
IRQ4 input
PDR9: PCR9: PMR9: PFCR:
Port data register 9 Port contol register 9 Port mode register 9 Port function control register
Figure B.8 (b) Port 9 Block Diagram (P92)
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Appendix
SBY
PWM module PWMn+1 output
VCC
PMR9 (PWMn+1) PDR9 (P9n) PCR9 (PCR9n)
Internal data bus
P9n
VSS
PDR9: PCR9: PMR9: n = 1, 0
Port data register 9 Port contol register 9 Port mode register 9
Figure B.8 (c) Port 9 Block Diagram (P91, P90)
SBY
VCC
PDRA (PAn) PCRA (PCRAn)
Internal data bus
PAn
VSS
PDRA: PCRA: n = 3 to 0
Port data register A Port contol register A
Figure B.9 Port A Block Diagram
Rev. 2.00 Jul. 04, 2007 Page 648 of 692 REJ09B0309-0200
Appendix
PBn
Internal data bus
A/D module
DEC
AMR3 to AMR0
VIN
n = 7 to 3
Figure B.10 (a) Port B Block Diagram (PB7 to PB3)
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Appendix
IRQm input
PMRB (IRQm)
PBn
Internal data bus
A/D module
DEC
AMR3 to AMR0
VIN
PMRB: n = 2 to 0
Port mode register B m = 3, 1, 0
Figure B.10 (b) Port B Block Diagram (PB2 to PB0)
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Appendix
SBY VCC
PCn PDRC (PCn)
VSS
PCRC (PCRCn)
PDRC: PCRC:
Port data register C
Port contol register C n = 7 to 0
Figure B.11 Port C Block Diagram (PC7 to PC0)
SBY VCC
PMRB (IRQ0) PMRE (IRQ0)
PE7
PMRE (TMIC) PDRE (PE7) PCRE (PCRE7)
VSS
Internal data bus
Timer C module TMIC input
PDRE: PCRE: PMRE: PMRB:
Port data register E Port contol register E Port mode register E Port mode register B
IRQ0 input
Figure B.12 (a) Port E Block Diagram (PE7)
Rev. 2.00 Jul. 04, 2007 Page 651 of 692 REJ09B0309-0200
Internal data bus
Appendix
SBY VCC
PMRE (UD) PE6 PDRE (PE6)
VSS
PCRE (PCRE6)
Internal data bus
Timer C module UD input
PDRE: PCRC: PMRE:
Port data register E Port contol register E Port mode register E
Figure B.12 (b) Port E Block Diagram (PE6)
SBY VCC
PFCR (SC32S) SPCR (SPC32) PDRE (PE5)
PE5
VSS
PCRE (PCRE5)
PDRE: PCRE: SPCR: PFCR:
Port data register E Port contol register E Serial port control register Port function control register
SPCR (SCINV3)
Internal data bus
SCI3_2 module
TXD32 output
Figure B.12 (c) Port E Block Diagram (PE5)
Rev. 2.00 Jul. 04, 2007 Page 652 of 692 REJ09B0309-0200
Appendix
SBY VCC
PE4
PFCR (SC32S)
VSS
PCRE (PCRE4)
PDRE: PCRE: SPCR: PFCR:
Port data register E Port contol register E Serial port control register Port function control register
SPCR (SCINV2)
Internal data bus
SCI3_2 module RXD32 input enable RXD32 input
PDRE (PE4)
Figure B.12 (d) Port E Block Diagram (PE4)
Rev. 2.00 Jul. 04, 2007 Page 653 of 692 REJ09B0309-0200
Appendix
SBY
VCC
PMRB (IRQ1) PE3 PMRE (IRQ1) PDRE (PE3) PCRE (PCRE3)
VSS
PFCR (SC32S)
Internal data bus
SCI3_2 module SCK32 input enable SCK32 output enable SCK32 output SCK32 input IRQ1 input
PDRE: PCRE: PMRE: PMRB: PFCR:
Port data register E Port contol register E Port mode register E Port mode register B Port function control register
Figure B.12 (e) Port E Block Diagram (PE3)
Rev. 2.00 Jul. 04, 2007 Page 654 of 692 REJ09B0309-0200
Appendix
SBY VCC
PE2
SPCR2 (SPC33)
VSS
PCRE (PCRE2)
PDRE: PCRE:
Port data register E Port contol register E
SPCR2 (SCINV5)
Internal data bus
PDRE (PE2)
SCI3_3 module
TXD33 output
SPCR2: Serial port control register 2
Figure B.12 (f) Port E Block Diagram (PE2)
SBY VCC
PE1
VSS
PCRE (PCRE1)
SPCR2 (SCINV4)
Internal data bus
SCI3_3 module RXD33 input enable RXD33 input
PDRE (PE1)
PDRE: PCRE:
Port data register E Port contol register E
SPCR2: Serial port control register 2
Figure B.12 (g) Port E Block Diagram (PE1)
Rev. 2.00 Jul. 04, 2007 Page 655 of 692 REJ09B0309-0200
Appendix
SBY
VCC
PMRB (IRQ3) PE0 PMRE (IRQ3) PDRE (PE0) PCRE (PCRE0)
VSS
Internal data bus
SCI3_3 module SCK33 input enable SCK33 output enable SCK33 output SCK33 input IRQ3 input
PDRE: PCRE: PMRE: PMRB:
Port data register E Port contol register E Port mode register E Port mode register B
Figure B.12 (h) Port E Block Diagram (PE0)
Rev. 2.00 Jul. 04, 2007 Page 656 of 692 REJ09B0309-0200
Appendix
SBY VCC
PFCR (SC31S) SPCR (SPC31)
Internal data bus
PF3
PDRF (PF3)
VSS
PCRF (PCRF3)
PDRF: PCRF: SPCR: PFCR:
Port data register F Port contol register F Serial port control register Port function control register
SPCR (SCINV1)
SCI3_1 module
TXD31/IrTXD output
Figure B.13 (a) Port F Block Diagram (PF3)
Rev. 2.00 Jul. 04, 2007 Page 657 of 692 REJ09B0309-0200
Appendix
SBY VCC
PF2
PFCR (SC32S) PDRF (PF2)
VSS
PCRF (PCRF2)
SPCR (SCINV0)
Internal data bus
SCI3_1 module RXD31/IrRXD input enable RXD31/IrRXD input
PDRF: PCRF: SPCR: PFCR:
Port data register F Port contol register F Serial port control register Port function control register
Figure B.13 (b) Port F Block Diagram (PF2)
Rev. 2.00 Jul. 04, 2007 Page 658 of 692 REJ09B0309-0200
Appendix
SBY
VCC
PMR9 (IRQ4) PF1 PMRF (IRQ4) PDRF (PF1) PCRF (PCRF1)
VSS
PFCR (SC31S)
Internal data bus
SCI3_1 module SCK31 input enable SCK31 output enable SCK31 output SCK31 input IRQ4 input
PDRF: PCRF: PMRF: PMR9: PFCR:
Port data register F Port contol register F Port mode register F Port mode register 9 Port function control register
Figure B.13 (c) Port F Block Diagram (PF1)
Rev. 2.00 Jul. 04, 2007 Page 659 of 692 REJ09B0309-0200
Appendix
SBY VCC
PMRF (TMIG) PF0 PDRF (PF0)
VSS
PCRF (PCRF0)
Internal data bus
Timer G module TMIG input
PDRF: PCRF: PMRF:
Port data register F Port contol register F Port mode register F
Figure B.13 (d) Port F Block Diagram (PF0)
Rev. 2.00 Jul. 04, 2007 Page 660 of 692 REJ09B0309-0200
Appendix
B.2
Port States in Each Operating State
Active Sleep (High-Speed/ (High-Speed/ Medium-Speed) Medium-Speed) Watch Retained Retained
Operating Mode
Reset
Subactive Subsleep Functioning Retained
Standby High impedance *1*2 High impedance *1*2 High impedance *1 High impedance *1 High impedance *1*2 High impedance *1*2 High impedance *1 High impedance *1 High impedance *1 High impedance *1
P16 to P10 High Functioning impedance P37, P36, P30 P32, P31 High Functioning impedance High Functioning impedance
Retained
Retained
Functioning Retained
Retained
Retained
Functioning Retained
P42 to P40 High Functioning impedance P57 to P50 High Functioning impedance P67 to P60 High Functioning impedance P77 to P70 High Functioning impedance P87 to P80 High Functioning impedance P93 to P90 High Functioning impedance PA3 to PA0 High Functioning impedance
Retained
Retained
Functioning Retained
Retained
Retained
Functioning Retained
Retained
Retained
Functioning Retained
Retained
Retained
Functioning Retained
Retained
Retained
Functioning Retained
Retained
Retained
Functioning Retained
Retained
Retained
Functioning Retained
Rev. 2.00 Jul. 04, 2007 Page 661 of 692 REJ09B0309-0200
Appendix Active Sleep (High-Speed/ (High-Speed/ Medium-Speed) Medium-Speed) Watch High impedance*3 Retained
Operating Mode
Reset
Subactive Subsleep
Standby
PB7 to PB0 High High impedance impedance*3 PC7 to PC0 High Functioning impedance PE7 to PE0 High Functioning impedance PF3 to PF0 High Functioning impedance
High High High High impedance impedance impedance impedance *3 *3 *1 Retained Functioning Retained High impedance *1 High impedance *1 High impedance *1
Retained
Retained
Functioning Retained
Retained
Retained
Functioning Retained
Notes: 1. Registers are retained and output level is high impedance. 2. High-level output when the pull-up MOS is turned on. 3. The pin selected by the CH3 to CH0 bits in AMR is connected to the A/D converter.
Rev. 2.00 Jul. 04, 2007 Page 662 of 692 REJ09B0309-0200
Appendix
C.
Product Part No. Lineup
Product Part No. Regular specifications Wide-range specifications Masked ROM version Regular specifications Wide-range specifications HD64F38099FP4 HD64F38099FP10 HD64F38099FP10W Model Marking F38099FP4 F38099FP10 F38099FP10 Package (Package Code) 100 pin LQFP (PLQP0100KB-A) 100 pin LQFP (PLQP0100KB-A) HD64338099FP 38099(***)FP 100 pin LQFP (PLQP0100KB-A) HD64338099FPW 38099(***)FP 100 pin LQFP (PLQP0100KB-A) HD64338098FP 38098(***)FP 100 pin LQFP (PLQP0100KB-A) HD64338098FPW 38098(***)FP 100 pin LQFP (PLQP0100KB-A)
Product Classification H8/38099 Flash memory version
H8/38098
Masked ROM version
Regular specifications Wide-range specifications
[Legend] (***): ROM code
Rev. 2.00 Jul. 04, 2007 Page 663 of 692 REJ09B0309-0200
D.
Appendix
E
*2
HE
c1
c
1 Index mark F
25
ZD
ZE
A
A2
c
e x
bp
A1
REJ09B0309-0200
RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g
HD *1 D 51
JEITA Package Code P-LQFP100-14x14-0.50
75
Package Dimensions
Rev. 2.00 Jul. 04, 2007 Page 664 of 692
50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
Reference Symbol
76
Dimension in Millimeters
Terminal cross section
100 26
D E A2 HD HE A A1 bp b1 c c1
L L1 Detail F
Figure D.1 Package Dimensions (PLQP0100KB-A)
y *3
e x y ZD ZE L L1
Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0
Main Revisions and Additions in this Edition
Item Section 1 Overview 1.1 Features * Compact package Modified Figure 1.2 Pin Assignment of 4 H8/38099 Group (PLQP0100KBA) Figure 1.3 Pin Assignment of H8/38099 Group (PTLG0113JAA) Table 1.1 PTLG0113JA-A Pin Correspondence Table 1.1 Pin Functions Section 2 CPU 2.8.3 Bit-Manipulation Instruction Section 3 Exception Handling 3.2.1 Reset Exception Handling 49 Modified
: 2. The reset exception handling vector address (H'000000 to H'000003) is read and transferred to the PC, and then program execution starts from the address indicated by the PC.
Page 2
Revisions (See Manual for Details) The description on the package, LGA-113, is deleted.
Deleted
Deleted 5 to 10 42 The column on the PTLG0113JA-A is deleted. The programs for executing the instruction are modified.
Section 4 Interrupt Controller 4.5 Interrupt Exception Handling Vector Table
73
Deleted
Table 4.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the mask level. Priorities within a module are fixed. Interrupt mask levels other than NMI and address break can be modified by IPR.
4.6 Operation
77
Modified
: 2. With referring to the INTM1 and INTM0 bits in INTM and the I bit in CCR, control the following. The interrupt request is held pending when the I bit is set to 1.
When the I bit is cleared to 0 and INTM1 bit is set to 1,
interrupts with mask level 1 or less are held pending.
Rev. 2.00 Jul. 04, 2007 Page 665 of 692 REJ09B0309-0200
Item Table 4.4 Interrupt Response Times (States)
Page Revisions (See Manual for Details) 81 Modified
No. Execution Status 1 Interrupt mask level determination Total Number of States 1 or 2*1 18 to 41
Notes: 1. One state in case of an internal interrupt (2 states in case of an external interrupt). 2. Prefetch after interrupt acceptance and interrupt handling routine prefetch. 3. Internal processing after interrupt acceptance and internal processing after vector fetch.
Section 5 Clock Pulse Generator 91 5.3.1 Connecting 32.768kHz/38.4-kHz Crystal Resonator Figure 5.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator 5.3.1 Connecting 32.76891 kHz/38.4-kHz Crystal Resonator
Modified
Equivalent Series Resistance 30 k (max.) 35 k (max.)
Added
1. When using a resonator other than the above, ensure optimal conditions by conducting sufficient evaluation of consistency in cooperation with the manufacturer of the resonator. Even if the above resonators or products equivalent to them are implemented, their oscillation characteristics are affected by the board design. Be sure to use the actual board to evaluate consistency as a system. 2. The consistency as a system has to be verified not only in a reset state (i.e., the RES pin is driven low) but also in a state where a reset state has been exited (i.e., the low-level RES signal has been driven high). Figure 5.6 shows the equivalent circuit of the crystal resonator.
Figure 5.6 Equivalent Circuit of 32.768-kHz Crystal Resonator
92
Added
CS LS X1 RS X2
CO
C O = 0.9 pF (typ.) R S = 50 k (typ.) W = 32.768 kHz/38.4kHz
Rev. 2.00 Jul. 04, 2007 Page 666 of 692 REJ09B0309-0200
Item 5.3.3 How to Input the External Clock 5.4.1 Prescaler S
Page Revisions (See Manual for Details) 93 94 The title of the section modified Deleted
... The output from prescaler S is shared by the on-chip peripheral modules. The division ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode and sleep mode (medium-speed), ...
5.5.1 Note on Resonators and Resonator Circuits
95
Modified
Resonator characteristics are closely related to board design. Therefore, resonators should be assigned after being carefully evaluated by the user in the masked ROM version and flash memory version, with referring to the examples shown in this section.
5.5.3 Definition of Oscillation Stabilization Wait Time 5.5.5 Note on the Oscillation Stabilization of Resonators 5.5.6 Note on Using Power-On Reset
97, 98 The description in this section is modified.
99 99
The title modified Modified
The power-on reset circuit in this LSI adjusts the reset clear time by the capacitor capacitance, which is externally connected to the RES pin. The external capacitor capacitance should be adjusted to secure the oscillation stabilization time before reset clearing. For details, refer to section 23, Power-On Reset Circuit.
Rev. 2.00 Jul. 04, 2007 Page 667 of 692 REJ09B0309-0200
Item Section 6 Power-Down Modes
Page Revisions (See Manual for Details) Modified
Bit Bit Name Description 6 5 4 STS2 STS1 STS0 Standby Timer Select 2 to 0 ... When an external clock is to be used, the minimum value (STS3 = 0, STS2 = 1, STS1 = 0, STS0 = 1) is recommended. When the onchip oscillator for the system clock is to be used, four states (STS3 = 1, STS2 = 1, STS1 = 0, STS0 = 1) are recommended. If a setting other than the recommended value is made, operation may start before the end of the wait time. Active Mode Clock Select 1 and 0 Select the operating clock frequency in active (medium-speed) mode and sleep (mediumspeed) mode. The MA1 and MA0 bits should be written to in active (high-speed) mode or subactive mode.
102, 6.1.1 System Control Register 1 103 (SYSCR1)
1 0
MA1 MA0
6.1.3 System Control Register 3 105 (SYSCR3)
Modified
Bit Bit Name Description 0 STS3 Standby Timer Select 3 ... When an external clock is to be used, the minimum value (STS3 = 0, STS2 = 1, STS1 = 0, STS0 = 1) is recommended. When the onchip oscillator for the system clock is to be used, four states (STS3 = 1, STS2 = 1, STS1 = 0, STS0 = 1) is recommended. If a setting other than the recommended value is made, operation may start before the end of the wait time.
Rev. 2.00 Jul. 04, 2007 Page 668 of 692 REJ09B0309-0200
Item
Page Revisions (See Manual for Details) Added *
1
6.1.4 Clock Halt Registers 1 to 3 107 (CKSTPR1 to CKSTPR3)
CKSTPR1
Bit Bit Name Description FROMCK Flash Memory Module Standby STP*1*3 Flash memory enters standby mode when this bit is cleared to 0. When the addresses H'000000 to H'0000FF of the flash memory space is accessed while this bit is set to 0, the RAM emulation function is enabled and the addresses H'FFFC00 to H'FFFCFF of the RAM space can be accessed. For details, see section 7.4, Using RAM to Emulate Flash Memory. The RAM emulation function is supported only by the F-ZTAT version.
109
Deleted
Notes: : 4. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0. However, the watchdog timer does not enter module standby mode and continues operating. When the watchdog timer stops operating and the WDON bit is cleared to 0 by software, this bit is valid and the watchdog timer enters module standby mode.
Rev. 2.00 Jul. 04, 2007 Page 669 of 692 REJ09B0309-0200
Item Figure 6.1 Mode Transition Diagram
Page Revisions (See Manual for Details) 111 Modified
Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure to enable the interrupt request.
Table 6.3 Internal State in Each Operating Mode
115
Modified
Active Mode MediumFunction System clock oscillator Subclock oscillator High-speed Functioning Functioning/ halted CPU Instructions RAM Registers I/O External interrupts NMI IRQ0 IRQ1 IRQ3 IRQ4 IRQAEC WKP0 to WKP7 Peripheral modules Timers F, G Timer C Functioning Functioning Functioning Functioning Functioning/ retained*
2
Sleep Mode Highspeed Functioning Functioning/ halted Halted Retained Mediumspeed Functioning Functioning/ halted Halted Retained Halted Retained Functioning Halted Retained Watch Mode Halted Functioning Subactive Mode Halted Functioning Subsleep Mode Halted Functioning Stand-by Mode Halted Functioning/ halted Halted Retained
speed Functioning Functioning/ halted Functioning
Functioning
Retained* Functioning Functioning Functioning Functioning Functioning Functioning Functioning
1
Functioning
Functioning/ retained*
2
Functioning/ retained*
2
Retained
Functioning/ retained*
3
Functioning/ retained*
3
Functioning/ retained*
3
Retained
Asynchronous event counter RTC
Functioning
Functioning
Functioning
Functioning
Functioning/ retained*
8
Functioning/ retained* Retained Functioning/ retained*
4 8
Functioning/ retained* Retained Functioning/ retained*
4 8
Retained
TPU WDT
Retained Functioning/ retained*
4
Retained Functioning/ retained* Reset
5
SCI3/IrDA
Reset
Functioning/ retained*
6
Functioning/ retained* Retained
6
IIC2 PWM A/D converter LCD
Retained
Retained
Retained
Functioning/ retained*
7
Functioning/ retained*
7
Functioning/ retained* Retained
7
Address break
Retained
Retained
Retained
Functioning
Notes: 1. .... 8.
Functions if the RTC operation is selected as a clock source. Halted and retained for the free-running counter.
6.2.2 Standby Mode
116
Modified
... However, as long as the rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. ...
Rev. 2.00 Jul. 04, 2007 Page 670 of 692 REJ09B0309-0200
Item 6.2.2 Standby Mode
Page Revisions (See Manual for Details) 116 Modified
... or the requested interrupt is disabled by the interrupt enable bit. When a reset source is generated in standby mode, the system clock oscillator and the on-chip oscillator for the system clock start. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high.
6.2.3 Watch Mode
117
Modified
... or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in watch mode, the system clock oscillator starts. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high.
6.2.4 Subsleep Mode
117
Modified
... or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in subsleep mode, the system clock oscillator starts. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high.
6.2.5 Subactive Mode
118
Modified
... on the combination of bits SSBY, LSON, and TMA3 in SYSCR1 and bits MSON and DTON in SYSCR2. Subactive mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in subactive mode, the system clock oscillator starts. The RES pin must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high. The operating frequency of subactive mode is selected from W/2, W/4, and W/8 by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution.
Rev. 2.00 Jul. 04, 2007 Page 671 of 692 REJ09B0309-0200
Item 6.2.6 Active (Medium-Speed) Mode 6.3 Direct Transition 6.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode
Page Revisions (See Manual for Details) 118 119 119 The description in this section is modified. The description in this section is modified. Added
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made to active (medium-speed) mode via sleep mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). : Example: When osc/8 is selected as the CPU operating clock after the transition Direct transition time = (2 + 1) x 1tosc + 14 x 8tosc = 115tosc For the legend of symbols used above, refer to section 26, Electrical Characteristics.
6.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode
120
Added
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY, TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). : Example: When w/8 is selected as the subactive operating clock after the transition Direct transition time = (2 + 1) x 1tosc + 14 x 8tw = 3tosc + 112tw For the legend of symbols used above, refer to section 26, Electrical Characteristics.
Rev. 2.00 Jul. 04, 2007 Page 672 of 692 REJ09B0309-0200
Item
Page Revisions (See Manual for Details) Added
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). : Example: When osc/8 is selected as the CPU operating clock before the transition Direct transition time = (2 + 1) x 8tosc + 14 x 1tosc = 38tosc For the legend of symbols used above, refer to section 26, Electrical Characteristics.
6.3.3 Direct Transition from 120 Active (Medium-Speed) Mode to Active (High-Speed) Mode
6.3.4 Direct Transition from 121 Active (Medium-Speed) Mode to Subactive Mode
Added
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY, LSON, and TMA3 bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). : Example: When osc/8 and w/8 are selected as the CPU operating clock before and after the transition, respectively Direct transition time = (2 + 1) x 8tosc + 14 x 8tw = 24tosc + 112tw For the legend of symbols used above, refer to section 26, Electrical Characteristics.
Rev. 2.00 Jul. 04, 2007 Page 673 of 692 REJ09B0309-0200
Item
Page Revisions (See Manual for Details) Added and modified
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (5). : Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + (Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states) x (tcyc after transition)...............................................(5) Example: When w/8 is selected as the CPU operating clock after the transition and wait time = 8192 states Direct transition time = (2 + 1) x 8tw + (8192 + 14) x1tosc = 24tw + 8206tosc For the legend of symbols used above, refer to section 26, Electrical Characteristics.
6.3.5 Direct Transition from 121 Subactive Mode to Active (HighSpeed) Mode
Rev. 2.00 Jul. 04, 2007 Page 674 of 692 REJ09B0309-0200
Item 6.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
Page Revisions (See Manual for Details) 122 Added
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (6). : Example: When w/8 and osc/8 are selected as the CPU operating clock before and after the transition, respectively, and wait time = 8192 states Direct transition time = (2 + 1) x 8tw + 8192 x 1tosc + 14 x 8tosc = 24tw + 8304tosc For the legend of symbols used above, refer to section 26, Electrical Characteristics.
Section 7 ROM Figure 7.4 Flow of RAM Emulation 7.9 Notes on Setting Module Standby Mode 147
Figure 7.4 and the description on the figure are deleted.
Modified
... Then the flash memory should be set to enter the module standby mode. When the RAM emulation is not in use, if an interrupt is generated in module standby mode, the vector address cannot be fetched. As a result, the program may run away. : When the RAM emulation is used (an interrupt vector is provided), if an interrupt is generated in module standby mode, the vector address can be set by assigning the interrupt vector to the RAM, and this prevents the program to run away. For details, see section 7.4, Using RAM to Emulate Flash Memory.
Rev. 2.00 Jul. 04, 2007 Page 675 of 692 REJ09B0309-0200
Item Section 9 I/O Ports 9.2.5 Pin Functions * P30/SCK32/TMOW/CLKOUT pin
Page Revisions (See Manual for Details) 165 Modified
SCR3_2 CKE1 0 CKE0 0 PCR3 PCR30 0 1 1 1 0 1 0 0 1 1 0 1 x P30 input pin P30 output pin SCK32 output pin SCK32 input pin Setting prohibited SCK32 output pin Setting prohibited SCK32 input pin Setting prohibited Pin Function
9.3.4 Pin Functions * P40/SCK31/TMIF pin
170
Modified
SCR3_1 CKE1 0 CKE0 0 PCR4 PCR40 0 1 1 1 0 1 0 0 1 1 0 1 x P40 input pin P40 output pin SCK31 output pin SCK31 input pin Setting prohibited SCK31 output pin Setting prohibited SCK31 input pin Setting prohibited Pin Function
9.4.5 Pin Functions * P57/WKP7/SEG8 to P54/WKP4/SEG5 pins
173
Modified
PCR5 PCR5n 0 1 0 1 x P5n input pin P5n output pin WKPn input pin Setting prohibited SEGn+1 output pin Pin Function
Rev. 2.00 Jul. 04, 2007 Page 676 of 692 REJ09B0309-0200
Item * P53/WKP3/SEG4 to P50/WKP0/SEG1 pins
Page Revisions (See Manual for Details) 173 Modified
PCR5 PCR5m 0 1 0 1 x P5m input pin P5m output pin WKPm input pin Setting prohibited SEGm+1 output pin Pin Function
9.8.4 Pin Functions * P92/PWM3/IRQ4 pin
185
Modified
PCR9 PCR92 0 1 x 0 1 P92 input pin P92 output pin PWM3 output pin IRQ4 input pin Setting prohibited Pin Function
9.10.3 Pin Functions * PB2/AN2/IRQ3 pin
193
Modified
AMR CH3 to CH0 Other than B'0110 B'0110 Other than B'0110 B'0110 PB2 input pin AN2 input pin IRQ3 input pin Setting prohibited Pin Function
*
PB1/AN1/IRQ1 pin
193
Modified
AMR CH3 to CH0 Other than B'0101 B'0101 Other than B'0101 B'0101 PB1 input pin AN1 input pin IRQ1 input pin Setting prohibited Pin Function
Rev. 2.00 Jul. 04, 2007 Page 677 of 692 REJ09B0309-0200
Item * PB0/AN0/IRQ0 pin
Page Revisions (See Manual for Details) 193 Modified
AMR CH3 to CH0 Other than B'0100 B'0100 Other than B'0100 B'0100 PB0 input pin AN0 input pin IRQ0 input pin Setting prohibited Pin Function
9.12.4 Pin Functions * PE3 (/SCK32/IRQ1) pin
200
Modified
SCR3_2 CKE1 x x CKE0 x x PCRE PCRE3 x 0 1 0 0 0 1 1 1 0 1 0 0 1 1 0 1 x IRQ1 input pin PE3 input pin PE3 output pin PE3 input pin PE3 output pin SCK32 output pin SCK32 input pin Setting prohibited SCK32 output pin Setting prohibited SCK32 input pin Setting prohibited Pin Function
*
PE0/SCK33 (/IRQ3) pin
201
Modified
SCR3_3 CKE1 x 0 CKE0 x 0 PCRE PCRE0 x 0 1 1 1 0 1 0 0 1 1 0 1 x IRQ3 input pin PE0 input pin PE0 output pin SCK33 output pin SCK33 input pin Setting prohibited SCK33 output pin Setting prohibited SCK33 input pin Setting prohibited Pin Function
Rev. 2.00 Jul. 04, 2007 Page 678 of 692 REJ09B0309-0200
Item 9.13.4 Pin Functions * PF1 (/SCK31/IRQ4) pin
Page Revisions (See Manual for Details) 205 Modified
SCR3_1 CKE1 x x CKE0 x x PCRF PCRF1 x 0 1 0 0 0 1 1 1 0 1 0 0 1 1 0 1 x IRQ4 input pin PF1 input pin PF1 output pin PF1 input pin PF1 output pin SCK31 output pin SCK31 input pin Setting prohibited SCK31 output pin Setting prohibited SCK31 input pin Setting prohibited Pin Function
9.16.1 How to Handle Unused Pin
210
Deleted
* If an unused pin is an output pin, it is recommended to handle it in one of the following ways: Set the output of the unused pin to high and pull it up to Vcc with an on-chip pull-up MOS.
Set the output of the unused pin to high and pull it up to
Vcc with an external resistor of approximately 100 k.
9.16.2 Input Characteristics Difference due to Pin Function
210
This section is newly added.
Rev. 2.00 Jul. 04, 2007 Page 679 of 692 REJ09B0309-0200
Item Section 10 Realtime Clock (RTC) 10.3.7 Clock Source Select Register (RTCCSR)
Page Revisions (See Manual for Details) 220 Modified
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than w/4 is selected, the RTC is disabled and operates as an 8-bit free running counter. Bit Bit Name Description 3 2 1 0 RCS3 RCS2 RCS1 RCS0 Clock Source Selection 0000: /8Free running counter operation 0001: /32Free running counter operation 0010: /128Free running counter operation 0011: /256Free running counter operation 0100: /512Free running counter operation 0101: /2048Free running counter operation 0110: /4096Free running counter operation 0111: /8192Free running counter operation 1000 : w/4RTC operation 1001 to 1111: Setting prohibited
10.4.1 Initial Settings of Registers after Power-On
222
Modified
The RTC registers that store second, minute, hour, and day-ofweek data, control registers, and interrupt registers are not initialized by a RES input, or by a reset source caused by a watchdog timer.
10.5 Interrupt Sources
224
Modified
... When using an interrupt, set the IENRTC (RTC interrupt request enable) bit in IENR1 to 1 last after other registers are set.
10.6.2 Note when Using RTC Interrupts Section 11 Timer C 11.1 Features
225 227
This section is newly added. Modified
* Up/down-counter switching is selected either by the register specification or the external input level specification.
Rev. 2.00 Jul. 04, 2007 Page 680 of 692 REJ09B0309-0200
Item 11.3.1 Timer Mode Register C (TMC)
Page Revisions (See Manual for Details) 229 Modified
Bit Bit Name Description 6 5 TMC6 TMC5 Counter Up/Down Control Specifies whether TCC functions as an upcounter or down-counter, or whether selection of counting up or down is controlled by the input signal level on the UD pin. 00: TCC is an up-counter 01: TCC is a down-counter 1x: Selection through the signal level on the UD pin UD pin input high: Down-counter UD pin input low: Up-counter
11.4.1 Interval Timer Operation
232
Modified
... TCC up/down-count control can be specified by bits TMC6 and TMC5 in TMC, or selected by the input signal level on the UD pin.
11.4.3 Event Counter Operation 233
Modified
Timer C can operate as an event counter, with the TMIC pin as the event input pin. External event counting is selected by setting bits TMC3 to TMC0 in the timer mode register C (TMC) to B'0111 or B'1111, and setting the TMIC bit in PMRE to 1. TCC counts up/down at the rising/falling edge of an external event signal input at the TMIC pin. The external event input signal is not counted correctly if it does not satisfy the high width or low width of the input pin.
11.4.4 TCC Up/Down Control by 233 the External Input Pin Section 12 Timer F 12.4.1 Timer F Operation (1) Operation in 16-Bit Timer Mode Figure 12.2 Count Timing for Internal Clock Operation Figure 12.3 Count Timing for External Event Operation 244 244 243
The section title is modified. Modified
... OCRF contents are constantly compared with TCF, and when both values satisfy the compare match condition, CMFH is set to 1 in TCSRF.
Added Added
Rev. 2.00 Jul. 04, 2007 Page 681 of 692 REJ09B0309-0200
Item Figure 12.4 TMOFH/TMOFL Output Timing Figure 12.5 TCF Clear Timing Figure 12.6 Compare Match Flag Set Timing 12.6.1 16-Bit Timer Mode
Page Revisions (See Manual for Details) 245 245 246 248 Modified Added Added Modified
... However, if the written data and the counter value match, there is a probability of a compare match signal being generated and not being generated.
12.6.2 8-Bit Timer Mode (1) TCFH, OCRFH
248
Modified
... However, even if the written data and the counter value match, there is a probability of a compare match signal being generated and not being generated.
(2) TCFL, OCRFL
249
Modified
... However, even if the written data and the counter value match, there is a probability of a compare match signal being generated and not being generated.
12.6.4 Timer Counter (TCF) Read/Write
251
Modified
When the internal clock W/4 is selected as the counter input clock in active (high-speed, medium-speed) mode, normal write is not performed on TCF. And when reading TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of 1. When reading or writing TCF in active (high-speed, mediumspeed) mode is needed, select the input clock except for W/4 before read/write is performed.
Section 13 Timer G Figure 13.4 Input Capture Input Timing (without Noise Cancellation Function) Figure 13.6 Timing of Input Capture by Input Capture Input Figure 13.7 TCG Clear Timing
262
Modified
263 264
Modified Modified
Rev. 2.00 Jul. 04, 2007 Page 682 of 692 REJ09B0309-0200
Item Section 14 16-Bit Timer Pulse Unit (TPU) 14.3.6 Timer Counter (TCNT)
Page Revisions (See Manual for Details) 285 Deleted
TCNT is a 16-bit readable/writable counter. The TPU has a total of two TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode.
Figure 14.2 16-Bit Register Access Operation [CPU TCNT (16 Bits)]
288
Modified
Module data bus
Upper 8 bits TCNT
Lower 8 bits
Figure 14.20 Example of PWM Mode Operation (3) 14.6 Interrupt Sources
304 305
Modified Modified
... Mask levels within a channel can be changed by the interrupt controller. For details, see section 4, Interrupt Controller.
14.8.12 Interrupts when Module 318 Standby Function is Used
Modified
If the module standby function is used when an interrupt has been requested, it will not be possible to clear the CPU interrupt source with the interrupt request enabled. Interrupts should therefore be disabled before using the module standby function.
14.8.13 Output Conditions for 0% Duty and 100% Duty
318
Added Modified
Notes: 1. When an asynchronous external event is input, the counter increments. In addition, when an overflow occurs, an interrupt is requested.
Section 15 Asynchronous Event 332 Counter (AEC) Table 15.3 Operating States of Asynchronous Event Counter
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Item Section 16 Watchdog Timer 16.2.1 Timer Control/Status Register WD1 (TCSRWD1)
Page Revisions (See Manual for Details) 338 Added
Bit Bit Name Description 0 WRST Watchdog Timer Reset Indicates whether a reset caused by the watchdog timer is generated. This bit is not cleared by a reset caused by the watchdog timer. [Setting condition] When TCWD overflows and an internal reset signal is generated
Section 17 Serial Communication Interface 3 (SCI3, IrDA) 17.3.12 Serial Extended Mode Register (SEMR)
377
Added
Bit Bit Name Description 3 ABCS Asynchronous Mode Basic Clock Select Selects the basic clock for one-bit interval in asynchronous mode. The ABCS setting is enabled in asynchronous mode (COM = 0 in SMR3) 0: Basic clock with a frequency 16 times the transfer rate 1: Basic clock with a frequency 8 times the transfer rate Clear this bit to 0 when the IrDA function is enabled.
Figure 17.19 IrDA Block Diagram 17.7.1 Transmission
401 402
Modified Modified
... According to the standard, the high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) + 1.08 s at maximum. For example, when the frequency of system clock is 10 MHz, being equal to or greater than 1.41 s, the high-level pulse width at minimum can be specified as 1.6 s.
17.7.2 Reception
403
Modified
... If a pulse has a high-level width of less than 1.41 s, the minimum width allowed, the pulse is not recognized.
Section 19 14-Bit PWM
433 to Entirely revised 440
Rev. 2.00 Jul. 04, 2007 Page 684 of 692 REJ09B0309-0200
Item Section 20 A/D Converter 20.3.1 A/D Result Register (ADRR) 20.7.3 Usage Notes
Page Revisions (See Manual for Details) 444 Modified
ADRR is a 16-bit read-only register that stores the results of A/D conversion. The data is stored in the upper 10 bits of ADRR. ADRR can be read by the CPU at any time, ...
454
Deleted
: 3. When A/D conversion is started after clearing module standby mode, wait for 10 clock cycles before starting A/D conversion. 4. Even when the resistor ladder is made operational by setting the LADS bit in ADSR, wait for 10 clocks before starting A/D conversion.
Section 21 21.3.1 LCD Port Control Register (LPCR)
458
Modified
Bit Bit Name Description 7 6 5 DTS1 DTS0 CMX Duty Cycle Select 1 and 0 Common Function Select The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used due to the selected duty. For details, see table 21.2.
21.3.4 LCD Trimming Register (LTRMR)
463
Modified
LTRMR adjusts the 3-V constant-voltage used for LCD drive power supply and the output voltage of 3-V constant-voltage power supply circuit.
Rev. 2.00 Jul. 04, 2007 Page 685 of 692 REJ09B0309-0200
Item 21.4.3 3-V Constant-Voltage Power Supply Circuit
Page Revisions (See Manual for Details) 473 Modified
... Before activating a step-up circuit, operate the LCD controller/driver, and set the duty cycle, pin function, display data, frame frequencies, etc. Insert a capacitance of 0.1 F between the C1 pin and C2 pin, and connect a capacitance of 0.1 F to each of V1, V2, and V3 pins.
474
Modified
Notes: : 4. The step-up circuit output voltage in the initial state is different in an individual device according to the manufacturing difference.
21.5 Usage Notes Section 22 I C Bus Interface 2 (IIC2) Figure 22.15 Receive Mode Operation Timing
2
477 506
Added Modified
7 8 Bit 7 1 Bit 0 2 Bit 1
Figure 22.17 Sample Flowchart for Master Transmit Mode
508
Modified
No
[14] STOP=1 ? Yes Set MST to 0 and TRS to 0 in ICCR1 Clear TDRE in ICSR End
[15]
22.7.3 Restriction on Transfer Rate Setting in Multimaster Operation 22.7.4 Restriction on the Use of Bit Manipulation Instructions for MST and TRS Setting in Multimaster Operation 22.7.5 Usage Note on Master Receive Mode
514
Added
515
Added
515
Added
Rev. 2.00 Jul. 04, 2007 Page 686 of 692 REJ09B0309-0200
Item Section 26 Electrical Characteristics Table 26.2 DC Characteristics
Page Revisions (See Manual for Details) 554 to Modified 561
Table 26.3 Control Signal Timing 562 to Modified 566 Table 26. 6 A/D Converter Characteristics Table 26.16 A/D Converter Characteristics 569 595 Modified
Notes: :
3. AISTOP2 is the current at a reset, in standby or watch mode while the A/D converter is idle, or in the module standby state. 570 Modified
Table 26.7 LCD Characteristics Table 26.10 Flash Memory Characteristics Table 26.12 DC Characteristics Table 26.13 Control Signal Timing Table 26.16 A/D Converter Characteristics
573 to Modified 575 580 to Modified 587 588 to Modified 591 594 to Modified 595 Modified Added Connecting a bypass capacitor is recommended for noise suppression.
Table 26.17 LCD Characteristics 596 26.8 Usage Note 602
Appendix C. Product Part No. Lineup
663
The list is modified. Deleted
Figure D.2 Package Dimensions 665 (PTLG0113JA-A)
Rev. 2.00 Jul. 04, 2007 Page 687 of 692 REJ09B0309-0200
Rev. 2.00 Jul. 04, 2007 Page 688 of 692 REJ09B0309-0200
Index
Numerics
16-bit timer mode ................................... 242 16-bit timer pulse unit............................. 271 8-bit timer mode ..................................... 243
D
Data reading procedure ........................... 223 Data transfer instructions .......................... 22
A
A/D converter ......................................... 441 Absolute address....................................... 33 Acknowledge .......................................... 496 Address break ......................................... 519 Addressing modes..................................... 32 Arithmetic operations instructions............ 23 Asynchronous event counter (AEC) ....... 319 Asynchronous mode ............................... 378
E
Effective address ....................................... 36 Effective address extension....................... 31 Erase/erase-verify ................................... 143 Erasing units ........................................... 128 Error protection....................................... 145 Exception handling ................................... 47
F
Flash memory.......................................... 127 Framing error .......................................... 386 Free-running count operation.................. 291
B
Bit manipulation instructions.................... 26 Bit rate .................................................... 361 Bit synchronous circuit ........................... 513 Block data transfer instructions ................ 30 Boot mode............................................... 134 Boot program.......................................... 133 Branch instructions ................................... 28 Break....................................................... 407
G
General registers ....................................... 15
H
Hardware protection................................ 145
C
Clock pulse generator ............................... 85 Clocked synchronous mode .................... 390 Clocked synchronous serial format......... 504 Condition field .......................................... 31 Condition-code register (CCR)................. 16 Counter operation ................................... 290 CPU .......................................................... 11
I
I/O ports .................................................. 151 I2C bus format ......................................... 495 I2C bus interface 2 (IIC2)........................ 479 Immediate ................................................. 34 Initial setting procedure .......................... 222 Input capture function ............................. 294 Input capture signal timing ..................... 308 Instruction set............................................ 21
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Interrupt mask bit (I)................................. 16 IrDA........................................................ 401
L
Large current ports...................................... 2 LCD controller/driver ............................. 455 LCD display............................................ 466 LCD RAM .............................................. 468 Logic operations instructions.................... 25
Power-on reset circuit ............................. 517 Prescaler W ............................................... 94 Program counter (PC) ............................... 16 Program/program-verify ......................... 140 Program-counter relative .......................... 34 Programmer mode................................... 146 Programming units.................................. 128 Programming/erasing in user program mode ....................................................... 137
R M
Mark state ............................................... 407 Memory indirect ....................................... 35 Memory map ............................................ 13 Module standby function ........................ 123 Multiprocessor communication function................................................... 396 RAM ....................................................... 149 Realtime clock (RTC) ............................. 211 Register direct ........................................... 33 Register field............................................. 31 Register indirect ........................................ 33 Register indirect with displacement .......... 33 Register indirect with post-increment ....... 33 Register indirect with pre-decrement ........ 33 Registers ABRKCR2 .................. 520, 528, 535, 542 ABRKSR2 .................. 522, 528, 535, 542 ADRR ......................... 444, 530, 537, 543 ADSR.......................... 446, 530, 537, 543 AEGSR ....................... 323, 529, 536, 542 AMR ........................... 444, 530, 537, 543 BAR2H ....................... 522, 528, 535, 542 BAR2L........................ 522, 528, 535, 542 BDR2H ....................... 522, 528, 535, 542 BDR2L........................ 522, 528, 535, 542 BGRMR .............................................. 465 BRR ............................ 361, 529, 536, 543 CKSTPR1 ................... 107, 532, 539, 545 CKSTPR2 ................... 108, 532, 539, 545 CKSTPR3 ........................................... 109 EBR1........................... 131, 526, 533, 540 EBR2................................................... 132 ECCR .......................... 324, 529, 536, 542 ECCSR........................ 325, 529, 536, 542
N
Noise canceler ........................................ 507
O
On-board programming modes............... 133 Operation field.......................................... 31 Output compare output timing................ 307 Overrun error .......................................... 386
P
Package....................................................... 2 Parity error.............................................. 386 Periodic count operation ......................... 291 Pin assignment............................................ 4 Power-down modes ................................ 101 Power-down states.................................. 146
Rev. 2.00 Jul. 04, 2007 Page 690 of 692 REJ09B0309-0200
ECH ............................ 327, 529, 536, 542 ECL............................. 327, 529, 536, 542 ECPWCR.................... 321, 528, 535, 542 ECPWDR.................... 322, 528, 536, 542 FENR .......................... 133, 526, 533, 540 FLMCR1..................... 129, 526, 533, 540 FLMCR2..................... 130, 526, 533, 540 FLPWCR .................... 132, 526, 533, 540 ICCR1......................... 482, 527, 534, 541 ICCR2......................... 485, 527, 534, 541 ICDRR ........................ 494, 528, 535, 541 ICDRS ................................................ 494 ICDRT ........................ 494, 528, 535, 541 ICIER.......................... 489, 527, 535, 541 ICMR .......................... 487, 527, 535, 541 ICRGF ................................................ 256 ICRGR ................................................ 256 ICSR ........................... 491, 528, 535, 541 IEGR............................. 61, 531, 538, 545 IENR............................. 63, 531, 538, 545 INTM............................ 71, 531, 539, 545 IPR................................ 70, 528, 535, 541 IrCR ............................ 376, 529, 536, 543 IRR ............................... 65, 531, 539, 545 IWPR ............................ 68, 532, 539, 545 LCR .................................................... 460 LCR2 .................................................. 462 LPCR .................................................. 458 LTRMR .............................................. 463 OCR ............................ 238, 530, 537, 543 OSCCR ......................... 87, 530, 537, 544 PCR1........................... 152, 531, 538, 544 PCR3........................... 161, 531, 538, 545 PCR4........................... 167, 531, 538, 545 PCR5........................... 171, 531, 538, 545 PCR6........................... 175, 531, 538, 545 PCR7........................... 179, 531, 538, 545 PCR8........................... 181, 531, 538, 545 PCR9........................... 184, 531, 538, 545 PCRA.......................... 187, 531, 538, 545
PCRC .................................................. 195 PCRE .................................................. 197 PCRF................................................... 203 PDR1........................... 152, 530, 538, 544 PDR3........................... 160, 530, 538, 544 PDR4........................... 166, 530, 538, 544 PDR5........................... 171, 531, 538, 544 PDR6........................... 175, 531, 538, 544 PDR7........................... 178, 531, 538, 544 PDR8........................... 181, 531, 538, 544 PDR9........................... 183, 531, 538, 544 PDRA.......................... 187, 531, 538, 544 PDRB .......................... 190, 531, 538, 544 PDRC .................................................. 194 PDRE .................................................. 196 PDRF .................................................. 202 PMR1 .......................... 153, 530, 537, 544 PMR3 .......................... 162, 530, 537, 544 PMR4 .......................... 168, 530, 537, 544 PMR5 .......................... 172, 530, 537, 544 PMR9 .......................... 184, 530, 537, 544 PMRB ......................... 191, 530, 537, 544 PMRE.................................................. 197 PMRF.................................................. 203 PUCR1 ........................ 153, 531, 538, 544 PUCR3 ........................ 162, 531, 538, 544 PUCR5 ........................ 172, 531, 538, 544 PUCR6 ........................ 176, 531, 538, 544 PWCR ......................... 435, 530, 537, 544 PWDR......................... 436, 530, 537, 544 RDR ............................ 352, 529, 536, 543 RHRDR....................... 215, 527, 534, 541 RMINDR..................... 214, 527, 534, 541 RSECDR ..................... 213, 527, 534, 541 RSR..................................................... 352 RTCCR1 ..................... 217, 527, 534, 541 RTCCR2 ..................... 219, 527, 534, 541 RTCCSR ..................... 220, 527, 534, 541 RTCFLG ..................... 221, 527, 534, 541 RWKDR...................... 216, 527, 534, 541
Rev. 2.00 Jul. 04, 2007 Page 691 of 692 REJ09B0309-0200
RWKDR ......................216, 527, 534, 541 SAR .............................494, 528, 535, 541 SCR3............................356, 529, 536, 542 SCR4............................415, 526, 533, 540 SCSR4 .........................418, 526, 533, 540 SMR.............................353, 529, 536, 542 SPCR ...........................373, 529, 536, 542 SSR ..............................358, 529, 536, 543 SUB32CR ......................86, 527, 534, 541 SYSCR1 ......................102, 531, 538, 545 SYSCR2 ......................104, 531, 538, 545 SYSCR3 ............................................. 105 TC................................237, 530, 537, 543 TCC .................................................... 231 TCG .................................................... 255 TCNT...........................285, 527, 533, 540 TCR .............................275, 526, 533, 540 TCRF ...........................239, 530, 537, 543 TCSRF.........................240, 530, 537, 543 TCSRWD1 ..................337, 529, 536, 543 TCSRWD2 ..................339, 529, 536, 543 TCWD .........................340, 530, 537, 543 TDR .............................352, 529, 536, 543 TGR .............................285, 527, 533, 540 TIER ............................283, 526, 533, 540 TIOR............................278, 526, 533, 540 TLC..................................................... 231 TMC ................................................... 229 TMDR..........................277, 526, 533, 540 TMG ................................................... 256 TMWD ........................341, 529, 536, 543 TSR..............................284, 526, 533, 540 TSTR ...........................286, 526, 533, 540 TSYR...........................287, 526, 533, 540 WEGR ...........................62, 528, 536, 542 ROM ....................................................... 127
S
Serial Communication Interface 3 (SCI3) ..................................................... 345 Serial Communication Interface 4 (SCI4) ..................................................... 413 Shift instructions ....................................... 25 Slave address........................................... 496 Sleep mode.............................................. 116 Software protection................................. 145 Stack pointer (SP) ..................................... 16 Standby mode ......................................... 116 Start condition......................................... 496 Stop condition ......................................... 496 Subactive mode....................................... 118 Subclock generator ................................... 91 Subsleep mode ........................................ 117 Synchronous operation............................ 296 System clock generator ............................. 88 System control instructions....................... 29
T
TCNT count timing................................. 306 Timer C ................................................... 227 Timer F ................................................... 235 Timer G................................................... 253 Toggle output.......................................... 292 Transfer rate............................................ 484
V
Vector address........................................... 48
W
Watchdog timer....................................... 335 Waveform output by compare match...... 292
Rev. 2.00 Jul. 04, 2007 Page 692 of 692 REJ09B0309-0200
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/38099 Group
Publication Date: Rev.1.00, Mar. 28, 2006 Rev.2.00, Jul. 04, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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